Change in coreboot[master]: soc/intel/tigerlake: Drops 100ms delay in TBT PCIe root ports _PS0 - coreboot-gerrit

2 Feb 2021


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Sukumar Ghorai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50086 )
Change subject: soc/intel/tigerlake: Drops 100ms delay in TBT PCIe root ports _PS0
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Patch Set 2: Code-Review+1
(1 comment)
Patchset:
PS2: 
Verified.
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ic392f9af6cd739507a80a4ca3fd126088b513304
Gerrit-Change-Number: 50086
Gerrit-PatchSet: 2
Gerrit-Owner: John Zhao john.zhao@intel.com
Gerrit-Reviewer: Duncan Laurie dlaurie@chromium.org
Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org
Gerrit-Reviewer: Sukumar Ghorai sukumar.ghorai@intel.com
Gerrit-Reviewer: Tim Wawrzynczak twawrzynczak@chromium.org
Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org
Gerrit-Attention: John Zhao john.zhao@intel.com
Gerrit-Comment-Date: Tue, 02 Feb 2021 17:49:51 +0000
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