Jiaxin Yu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32458
Change subject: mediatek/mt8183: Init audio related clock ......................................................................
mediatek/mt8183: Init audio related clock
Enable audio hoping clock and intbus clock and infra clock. Needed by playback beep sound in firmware.
BUG=b:117254418 BRANCH=none TEST=Build pass and verified on kukui p1 board
Change-Id: I88060d9796cc23ad7f524943f36869e1ec85073d Signed-off-by: Jiaxin Yu jiaxin.yu@mediatek.com --- M src/soc/mediatek/mt8183/pll.c 1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/32458/1
diff --git a/src/soc/mediatek/mt8183/pll.c b/src/soc/mediatek/mt8183/pll.c index 61aa2de..51c8774 100644 --- a/src/soc/mediatek/mt8183/pll.c +++ b/src/soc/mediatek/mt8183/pll.c @@ -356,4 +356,10 @@
/* enable [14] dramc_pll104m_ck */ setbits_le32(&mtk_topckgen->clk_misc_cfg_0, 1 << 14); + + /* enable audio needed */ + setbits_le32(&mtk_topckgen->clk_cfg_5_clr, 1 << 7); + setbits_le32(&mtk_topckgen->clk_cfg_5_clr, 1 << 15); + setbits_le32(&mt8183_infracfg->module_sw_cg_1_clr, 1 << 25); + setbits_le32(&mt8183_infracfg->module_sw_cg_2_clr, 1 << 4); }
Jiaxin Yu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32458 )
Change subject: mediatek/mt8183: Init audio related clock ......................................................................
Patch Set 1:
refer to: https://chromium-review.googlesource.com/c/chromiumos/platform/depthcharge/+...
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32458 )
Change subject: mediatek/mt8183: Init audio related clock ......................................................................
Patch Set 1:
(4 comments)
I
https://review.coreboot.org/#/c/32458/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/32458/1//COMMIT_MSG@9 PS1, Line 9: and replace with ','
https://review.coreboot.org/#/c/32458/1//COMMIT_MSG@9 PS1, Line 9: hoping is this a typo or correct name?
https://review.coreboot.org/#/c/32458/1//COMMIT_MSG@10 PS1, Line 10: playback beep sound audio playback
https://review.coreboot.org/#/c/32458/1/src/soc/mediatek/mt8183/pll.c File src/soc/mediatek/mt8183/pll.c:
https://review.coreboot.org/#/c/32458/1/src/soc/mediatek/mt8183/pll.c@361 PS1, Line 361: setbits_le32 The comment gave 3 (hoping, intbus and infra) but here the settings only do 2 set (or 4 clocks).
I think it'll be more clear if you have some comments for which line is setting what.
Hello Julius Werner, You-Cheng Syu, Tristan Hsieh, Hung-Te Lin, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32458
to look at the new patch set (#2).
Change subject: mediatek/mt8183: Init audio related clock ......................................................................
mediatek/mt8183: Init audio related clock
Enable audio clock, intbus clock, infra clock and mtkaif 26m clock.Needed by audio playback in firmware.
BUG=b:117254418 BRANCH=none TEST=Build pass and verified on kukui p1 board
Change-Id: I88060d9796cc23ad7f524943f36869e1ec85073d Signed-off-by: Jiaxin Yu jiaxin.yu@mediatek.com --- M src/soc/mediatek/mt8183/pll.c 1 file changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/32458/2
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32458 )
Change subject: mediatek/mt8183: Init audio related clock ......................................................................
Patch Set 2: Code-Review+2
Jiaxin Yu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32458 )
Change subject: mediatek/mt8183: Init audio related clock ......................................................................
Patch Set 2:
(4 comments)
Hi Hung-Te,please help to review again,thanks.
https://review.coreboot.org/#/c/32458/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/32458/1//COMMIT_MSG@9 PS1, Line 9: and
replace with ','
Done
https://review.coreboot.org/#/c/32458/1//COMMIT_MSG@9 PS1, Line 9: hoping
is this a typo or correct name?
Done
https://review.coreboot.org/#/c/32458/1//COMMIT_MSG@10 PS1, Line 10: playback beep sound
audio playback
Done
https://review.coreboot.org/#/c/32458/1/src/soc/mediatek/mt8183/pll.c File src/soc/mediatek/mt8183/pll.c:
https://review.coreboot.org/#/c/32458/1/src/soc/mediatek/mt8183/pll.c@361 PS1, Line 361: setbits_le32
The comment gave 3 (hoping, intbus and infra) but here the settings only do 2 set (or 4 clocks). […]
Done
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32458 )
Change subject: mediatek/mt8183: Init audio related clock ......................................................................
mediatek/mt8183: Init audio related clock
Enable audio clock, intbus clock, infra clock and mtkaif 26m clock.Needed by audio playback in firmware.
BUG=b:117254418 BRANCH=none TEST=Build pass and verified on kukui p1 board
Change-Id: I88060d9796cc23ad7f524943f36869e1ec85073d Signed-off-by: Jiaxin Yu jiaxin.yu@mediatek.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/32458 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Hung-Te Lin hungte@chromium.org --- M src/soc/mediatek/mt8183/pll.c 1 file changed, 12 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, approved
diff --git a/src/soc/mediatek/mt8183/pll.c b/src/soc/mediatek/mt8183/pll.c index 61aa2de..8608b4a 100644 --- a/src/soc/mediatek/mt8183/pll.c +++ b/src/soc/mediatek/mt8183/pll.c @@ -356,4 +356,16 @@
/* enable [14] dramc_pll104m_ck */ setbits_le32(&mtk_topckgen->clk_misc_cfg_0, 1 << 14); + + /* enable audio clock */ + setbits_le32(&mtk_topckgen->clk_cfg_5_clr, 1 << 7); + + /* enable intbus clock */ + setbits_le32(&mtk_topckgen->clk_cfg_5_clr, 1 << 15); + + /* enable infra clock */ + setbits_le32(&mt8183_infracfg->module_sw_cg_1_clr, 1 << 25); + + /* enable mtkaif 26m clock */ + setbits_le32(&mt8183_infracfg->module_sw_cg_2_clr, 1 << 4); }
-
Hung-Te Lin (Code Review) -
Jiaxin Yu (Code Review)
-
Patrick Georgi (Code Review)