Change in coreboot[master]: cpu/intel/common: use lapicid api

[Angel Pons (Code Review)]

Attention is currently required from: Lance Zhao, Nico Huber, Jamie Ryu, Furquan Shaikh, Wonkyu Kim, Ravishankar Sarawadi, Subrata Banik, Srinidhi N Kaushik, Raj Astekar, Patrick Rudolph.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51725 )

Change subject: cpu/intel/common: use lapicid api
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Patch Set 11:

(1 comment)

File src/cpu/intel/common/hyperthreading.c:

https://review.coreboot.org/c/coreboot/+/51725/comment/f3cdb125_83c3ddff 
PS11, Line 26: 	apic_ids = lapicid();
> The SDM says this is the "maximum number of addressable IDs for logical processors in this physical  […]

Reading further: in x2APIC mode, this would need to be done using CPUID leaf 0xb (or 0x1f). One would use EAX bits 4..0 from sub-leaf 0 (SMT level) to know how many x2APIC ID bits correspond to SMT level, and use this to know if a logical processor is an HT sibling.

I haven't tested it, but this should work for x2APIC:

if (x2apic) {
    if (cpuid_eax(0) >= 0xb) {
    	result = cpuid_ext(0xb, 0);
    	const uint32_t div = 1 << (result.eax & 0x1f);
    	if (div == 0)
    		return false;

return result.edx % div > 0;
    }
 }