Change in coreboot[master]: mb/intel/adlrvp: Configure GPIOs for Alder Lake-N

[Subrata Banik (Code Review)]

Attention is currently required from: Anilkumar N, Maulik V Vaghela, Kangheui Won, Tim Wawrzynczak, Rizwan Qureshi, Subrata Banik, Sridhar Siricilla, Krishna P Bhat D, Usha P.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59937 )

Change subject: mb/intel/adlrvp: Configure GPIOs for Alder Lake-N
......................................................................

Patch Set 10: Code-Review+1

(2 comments)

File src/mainboard/intel/adlrvp/Makefile.inc:

https://review.coreboot.org/c/coreboot/+/59937/comment/1666eb7f_f0d4cc96 
PS10, Line 12: ramstage-y += gpio_n.c
this is good but I will try to select specific file for ADL-P/M and N and error out if any design missed to select the PCH Kconfig in proper.

File src/mainboard/intel/adlrvp/gpio_n.c:

https://review.coreboot.org/c/coreboot/+/59937/comment/517becf1_6d931be2 
PS10, Line 8: static
@Usha: one request if below GPIOs doesn't have any particular order then I would prefer to club those as well.

1. All NF GPIO at first basically those are SoC default PIN programming
2. GPIOs that we configure based on board design.