Change in coreboot[master]: mb/google/octopus/variants/fleex: Remove NC GPIO_138 and GPIO_139 set...
John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35881 )
Change subject: mb/google/octopus/variants/fleex: Remove NC GPIO_138 and GPIO_139 setting to fix EMR function ......................................................................
mb/google/octopus/variants/fleex: Remove NC GPIO_138 and GPIO_139 setting to fix EMR function
Update GPIO_138 and GPIO_139 setting to fix EMR function.
BUG=b:141729962,b:141281846 BRANCH=octopus TEST=verify EMR function in Grob360S.
Change-Id: I28cef592374fb4aeee2f3d3010cc0e237d62a2fd Signed-off-by: John Su john_su@compal.corp-partner.google.com --- M src/mainboard/google/octopus/variants/fleex/gpio.c 1 file changed, 0 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/35881/1
diff --git a/src/mainboard/google/octopus/variants/fleex/gpio.c b/src/mainboard/google/octopus/variants/fleex/gpio.c index a1e02d2..b7dbd92 100644 --- a/src/mainboard/google/octopus/variants/fleex/gpio.c +++ b/src/mainboard/google/octopus/variants/fleex/gpio.c @@ -26,8 +26,6 @@ PAD_NC(GPIO_67, UP_20K), PAD_NC(GPIO_117, UP_20K),
- PAD_NC(GPIO_138, UP_20K), - PAD_NC(GPIO_139, UP_20K), /* GPIO_140 -- PEN_RESET */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_140, 0, DEEP, NONE, Tx1RxDCRx0, DISPUPD), PAD_NC(GPIO_143, UP_20K),
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35881 )
Change subject: mb/google/octopus/variants/fleex: Remove NC GPIO_138 and GPIO_139 setting to fix EMR function ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35881/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35881/1//COMMIT_MSG@7 PS1, Line 7: mb/google/octopus/variants/fleex: Remove NC GPIO_138 and GPIO_139 setting to fix EMR function Too long. Maybe just:
Update GPIOs to fix EMR
Marco Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35881 )
Change subject: mb/google/octopus/variants/fleex: Remove NC GPIO_138 and GPIO_139 setting to fix EMR function ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35881/1/src/mainboard/google/octopu... File src/mainboard/google/octopus/variants/fleex/gpio.c:
https://review.coreboot.org/c/coreboot/+/35881/1/src/mainboard/google/octopu... PS1, Line 29: PAD_NC(GPIO_138, UP_20K), It seems to me there is no one leveraged GPIO_138?
https://review.coreboot.org/c/coreboot/+/35881/1/src/mainboard/google/octopu... PS1, Line 32: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_140, 0, DEEP, NONE, Tx1RxDCRx0, DISPUPD), I checked the original review comment but it is still wried to me that - you put default state as low ->NMOS -> high then PEN_RESET_ODL is not active so chip is not in RESET state (???) during the boot up. - you set IOSTATE to high -> NMOS -> low so PEN_RESET_ODL is in active which hold chip is RESET state.
Hello Karthik Ramasubramanian, Marco Chen, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35881
to look at the new patch set (#2).
Change subject: mb/google/octopus/variants/fleex: Update GPIOs to fix EMR ......................................................................
mb/google/octopus/variants/fleex: Update GPIOs to fix EMR
Update GPIO_138 and GPIO_139 setting to fix EMR function.
BUG=b:141729962,b:141281846 BRANCH=octopus TEST=verify EMR function in Grob360S.
Change-Id: I28cef592374fb4aeee2f3d3010cc0e237d62a2fd Signed-off-by: John Su john_su@compal.corp-partner.google.com --- M src/mainboard/google/octopus/variants/fleex/gpio.c 1 file changed, 0 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/35881/2
John Su has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35881 )
Change subject: mb/google/octopus/variants/fleex: Update GPIOs to fix EMR ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35881/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35881/1//COMMIT_MSG@7 PS1, Line 7: mb/google/octopus/variants/fleex: Remove NC GPIO_138 and GPIO_139 setting to fix EMR function
Too long. Maybe just: […]
Done
John Su has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35881 )
Change subject: mb/google/octopus/variants/fleex: Update GPIOs to fix EMR ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35881/1/src/mainboard/google/octopu... File src/mainboard/google/octopus/variants/fleex/gpio.c:
https://review.coreboot.org/c/coreboot/+/35881/1/src/mainboard/google/octopu... PS1, Line 29: PAD_NC(GPIO_138, UP_20K),
It seems to me there is no one leveraged GPIO_138?
The PEN_PDCT_ODL is leveraged GPIO_138.
https://review.coreboot.org/c/coreboot/+/35881/1/src/mainboard/google/octopu... PS1, Line 32: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_140, 0, DEEP, NONE, Tx1RxDCRx0, DISPUPD),
I checked the original review comment but it is still wried to me that […]
There is an external inverter on the PEN_RESET_ODL. Therefore, the reset and power on sequence are both fine in the EMR function.
Marco Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35881 )
Change subject: mb/google/octopus/variants/fleex: Update GPIOs to fix EMR ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35881/1/src/mainboard/google/octopu... File src/mainboard/google/octopus/variants/fleex/gpio.c:
https://review.coreboot.org/c/coreboot/+/35881/1/src/mainboard/google/octopu... PS1, Line 29: PAD_NC(GPIO_138, UP_20K),
The PEN_PDCT_ODL is leveraged GPIO_138.
I can understand it is physically connected to GPIO_138 but what I mean is there is not FW or kernel driver or SW used this pin?
https://review.coreboot.org/c/coreboot/+/35881/1/src/mainboard/google/octopu... PS1, Line 32: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_140, 0, DEEP, NONE, Tx1RxDCRx0, DISPUPD),
There is an external inverter on the PEN_RESET_ODL. […]
I know there is an external inverter on the PEN_RESET_ODL and this is why overridetree.cb shows [1] (ACTIVE_HIGH). And the power sequence currently should be looked like (from acpi_device_add_power_res())
power on DUT -> GPIO_140 LOW (chip not in reset state) -> (boot to kernel) -> GPIO_140 HIGH (chip in reset state) -> (no enable gpio) -> GPIO_140 LOW (chip leave in reset state) -> (no stop gpio)
Then you can see in case of cold boot, 1. chip should be kept in reset state in coreboot stage but it is not 2. in kernel side, the GPIO_140 High to low is without delay so I doubt it's pulse width might be not enough?
[1] "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)"
John Su has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35881 )
Change subject: mb/google/octopus/variants/fleex: Update GPIOs to fix EMR ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35881/1/src/mainboard/google/octopu... File src/mainboard/google/octopus/variants/fleex/gpio.c:
https://review.coreboot.org/c/coreboot/+/35881/1/src/mainboard/google/octopu... PS1, Line 32: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_140, 0, DEEP, NONE, Tx1RxDCRx0, DISPUPD),
I know there is an external inverter on the PEN_RESET_ODL and this is why overridetree. […]
According schematic and specification, normal keep logic “Low”, when active EMR warm reset change to logic “High”. In this condition, we are the same setting with amption variant.(https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/refs/hea...)
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35881 )
Change subject: mb/google/octopus/variants/fleex: Update GPIOs to fix EMR ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35881/1/src/mainboard/google/octopu... File src/mainboard/google/octopus/variants/fleex/gpio.c:
https://review.coreboot.org/c/coreboot/+/35881/1/src/mainboard/google/octopu... PS1, Line 32: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_140, 0, DEEP, NONE, Tx1RxDCRx0, DISPUPD),
According schematic and specification, normal keep logic “Low”, when active EMR warm reset change to […]
Agree, we should invert default value against baseboard value since we have invert circuit.
John Su has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35881 )
Change subject: mb/google/octopus/variants/fleex: Update GPIOs to fix EMR ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35881/1/src/mainboard/google/octopu... File src/mainboard/google/octopus/variants/fleex/gpio.c:
https://review.coreboot.org/c/coreboot/+/35881/1/src/mainboard/google/octopu... PS1, Line 29: PAD_NC(GPIO_138, UP_20K),
I can understand it is physically connected to GPIO_138 but what I mean is there is not FW or kernel […]
https://partnerissuetracker.corp.google.com/issues/141729962#comment18
Marco Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35881 )
Change subject: mb/google/octopus/variants/fleex: Update GPIOs to fix EMR ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35881/1/src/mainboard/google/octopu... File src/mainboard/google/octopus/variants/fleex/gpio.c:
https://review.coreboot.org/c/coreboot/+/35881/1/src/mainboard/google/octopu... PS1, Line 29: PAD_NC(GPIO_138, UP_20K),
The comment still mention about physical connection only so I can understand we need the PU. But I don't see this GPIO is hook to any ACPI or FW to control?
https://review.coreboot.org/c/coreboot/+/35881/1/src/mainboard/google/octopu... PS1, Line 32: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_140, 0, DEEP, NONE, Tx1RxDCRx0, DISPUPD),
Agree, we should invert default value against baseboard value since we have invert circuit.
The external converter you point is "PMZ370UNE Q83", right? In reference board - yorp design, there is a Q83 PEN@PJE138K as well. As a result, both yorp (baseboard) and grob360s have inverter between pen_reset and pen_reset_odl.
John Su has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35881 )
Change subject: mb/google/octopus/variants/fleex: Update GPIOs to fix EMR ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35881/1/src/mainboard/google/octopu... File src/mainboard/google/octopus/variants/fleex/gpio.c:
https://review.coreboot.org/c/coreboot/+/35881/1/src/mainboard/google/octopu... PS1, Line 32: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_140, 0, DEEP, NONE, Tx1RxDCRx0, DISPUPD),
The external converter you point is "PMZ370UNE Q83", right? In reference board - yorp design, there […]
Yes, it’s and EE have confirmed it same as yorp.
Marco Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35881 )
Change subject: mb/google/octopus/variants/fleex: Update GPIOs to fix EMR ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35881/1/src/mainboard/google/octopu... File src/mainboard/google/octopus/variants/fleex/gpio.c:
https://review.coreboot.org/c/coreboot/+/35881/1/src/mainboard/google/octopu... PS1, Line 32: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_140, 0, DEEP, NONE, Tx1RxDCRx0, DISPUPD),
Yes, it’s and EE have confirmed it same as yorp.
Thanks for the prompt reply. Then if both of grob360s and yorp have "inverter" then what is the difference made grob360s set to 0 but baseboard - yorp set to 1?
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35881 )
Change subject: mb/google/octopus/variants/fleex: Update GPIOs to fix EMR ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35881/1/src/mainboard/google/octopu... File src/mainboard/google/octopus/variants/fleex/gpio.c:
https://review.coreboot.org/c/coreboot/+/35881/1/src/mainboard/google/octopu... PS1, Line 32: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_140, 0, DEEP, NONE, Tx1RxDCRx0, DISPUPD),
Thanks for the prompt reply. […]
In general, if RST pin is active HIGH, we will set it low in gpio.c and let ACPI driver in charge the power sequence include enable pin.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35881 )
Change subject: mb/google/octopus/variants/fleex: Update GPIOs to fix EMR ......................................................................
Patch Set 2:
(1 comment)
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35881/1/src/mainboard/google/octopu... File src/mainboard/google/octopus/variants/fleex/gpio.c:
https://review.coreboot.org/c/coreboot/+/35881/1/src/mainboard/google/octopu... PS1, Line 32: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_140, 0, DEEP, NONE, Tx1RxDCRx0, DISPUPD),
In general, if RST pin is active HIGH, we will set it low in gpio. […]
I checked some project, it's not consist with all. Some set the same, some set the opposite.
Marco Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35881 )
Change subject: mb/google/octopus/variants/fleex: Update GPIOs to fix EMR ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35881/1/src/mainboard/google/octopu... File src/mainboard/google/octopus/variants/fleex/gpio.c:
https://review.coreboot.org/c/coreboot/+/35881/1/src/mainboard/google/octopu... PS1, Line 32: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_140, 0, DEEP, NONE, Tx1RxDCRx0, DISPUPD),
I checked some project, it's not consist with all. Some set the same, some set the opposite.
If so, I would suggest to follow Octopus - yorp baseboard design because there are a lot of projects validated original design and setting already except you have good reason to support your decision. The original reason - inverter is not valid because all projects derived from yorp all have inverter as well.
On the other hand, if you refer to acpi_device_add_power_res() of coreboot then you will notice that in _ON, there is no delay between enable reset pin and disable reset pin. As a result, if your coreboot setting set reset pin as disabled then I doubt the enable state of reset pin is very short and might not apply the spec? Instead if set initial reset pin as enabled in coreboot then there is a native timing to keep it as enabled from booting coreboot to kernel then the enabled timing will be long enough.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35881 )
Change subject: mb/google/octopus/variants/fleex: Update GPIOs to fix EMR ......................................................................
Patch Set 2:
Patch Set 2:
(1 comment)
It add delay based on enable_delay_ms between enable and disable reset, I think we miss this in device tree. ELAN0001 and WDHT0002 have this.
Marco Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35881 )
Change subject: mb/google/octopus/variants/fleex: Update GPIOs to fix EMR ......................................................................
Patch Set 2:
Patch Set 2:
Patch Set 2:
(1 comment)
It add delay based on enable_delay_ms between enable and disable reset, I think we miss this in device tree. ELAN0001 and WDHT0002 have this.
Nice catch since EN_PP3300_TOUCHSCREEN control the power of stylus and if you add it as enable pin and add delay as well then it will be good to me. But curious about why without it the power of stylus is still enabled currently.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35881 )
Change subject: mb/google/octopus/variants/fleex: Update GPIOs to fix EMR ......................................................................
Patch Set 2:
Patch Set 2:
Patch Set 2:
Patch Set 2:
(1 comment)
It add delay based on enable_delay_ms between enable and disable reset, I think we miss this in device tree. ELAN0001 and WDHT0002 have this.
Nice catch since EN_PP3300_TOUCHSCREEN control the power of stylus and if you add it as enable pin and add delay as well then it will be good to me. But curious about why without it the power of stylus is still enabled currently.
That's true and HW measure power sequence is Pass. Kind of weird.
Marco Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35881 )
Change subject: mb/google/octopus/variants/fleex: Update GPIOs to fix EMR ......................................................................
Patch Set 2:
On the other hand, if you want to add the enable pin for stylus then we need to be careful about multiple components (drivers) control the same EN_PP3300_TOUCHSCREEN. In this case, need to verify whether the power sequence will be conflict between touchscreen and stylus. For example, in _OFF sequence stylus might cut the power before touchscreen did originally.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35881 )
Change subject: mb/google/octopus/variants/fleex: Update GPIOs to fix EMR ......................................................................
Patch Set 2:
Patch Set 2:
On the other hand, if you want to add the enable pin for stylus then we need to be careful about multiple components (drivers) control the same EN_PP3300_TOUCHSCREEN. In this case, need to verify whether the power sequence will be conflict between touchscreen and stylus. For example, in _OFF sequence stylus might cut the power before touchscreen did originally.
Oh. yes. You remind me EMR power is come from touch board. I think enable RST during boot up can help this because there is no independent power pin. If we just want add delay we may use the dummy pin as enable pin which won't broken the touch screen sequence.
Marco Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35881 )
Change subject: mb/google/octopus/variants/fleex: Update GPIOs to fix EMR ......................................................................
Patch Set 2:
Patch Set 2: Oh. yes. You remind me EMR power is come from touch board. I think enable RST during boot up can help this because there is no independent power pin. If we just want add delay we may use the dummy pin as enable pin which won't broken the touch screen sequence.
Then enabling RST pin in coreboot would be simple and align baseboard design.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35881 )
Change subject: mb/google/octopus/variants/fleex: Update GPIOs to fix EMR ......................................................................
Patch Set 2:
Patch Set 2:
Patch Set 2: Oh. yes. You remind me EMR power is come from touch board. I think enable RST during boot up can help this because there is no independent power pin. If we just want add delay we may use the dummy pin as enable pin which won't broken the touch screen sequence.
Then enabling RST pin in coreboot would be simple and align baseboard design.
That's okay to me. I miss the EMR doesn't have the enable pin. :)
Hello Karthik Ramasubramanian, Justin TerAvest, Marco Chen, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35881
to look at the new patch set (#3).
Change subject: mb/google/octopus/variants/fleex: Update GPIOs to fix EMR ......................................................................
mb/google/octopus/variants/fleex: Update GPIOs to fix EMR
Update GPIO_138 and GPIO_139 setting to fix EMR function.
BUG=b:141729962,b:141281846 BRANCH=octopus TEST=verify EMR function in Grob360S.
Change-Id: I28cef592374fb4aeee2f3d3010cc0e237d62a2fd Signed-off-by: John Su john_su@compal.corp-partner.google.com --- M src/mainboard/google/octopus/variants/fleex/gpio.c 1 file changed, 0 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/35881/3
Marco Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35881 )
Change subject: mb/google/octopus/variants/fleex: Update GPIOs to fix EMR ......................................................................
Patch Set 3: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/35881/1/src/mainboard/google/octopu... File src/mainboard/google/octopus/variants/fleex/gpio.c:
https://review.coreboot.org/c/coreboot/+/35881/1/src/mainboard/google/octopu... PS1, Line 29: PAD_NC(GPIO_138, UP_20K),
The comment still mention about physical connection only so I can understand we need the PU. […]
Seems to be no harmful if we follow the baseboard gpio so would be fine with it.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35881 )
Change subject: mb/google/octopus/variants/fleex: Update GPIOs to fix EMR ......................................................................
Patch Set 3:
(2 comments)
Thanks. Please help cherry-pick to ToT.
https://review.coreboot.org/c/coreboot/+/35881/1/src/mainboard/google/octopu... File src/mainboard/google/octopus/variants/fleex/gpio.c:
https://review.coreboot.org/c/coreboot/+/35881/1/src/mainboard/google/octopu... PS1, Line 29: PAD_NC(GPIO_138, UP_20K),
Seems to be no harmful if we follow the baseboard gpio so would be fine with it.
Ack
https://review.coreboot.org/c/coreboot/+/35881/1/src/mainboard/google/octopu... PS1, Line 32: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_140, 0, DEEP, NONE, Tx1RxDCRx0, DISPUPD),
If so, I would suggest to follow Octopus - yorp baseboard design because there are a lot of projects […]
Ack
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35881 )
Change subject: mb/google/octopus/variants/fleex: Update GPIOs to fix EMR ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35881/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35881/1//COMMIT_MSG@7 PS1, Line 7: mb/google/octopus/variants/fleex: Remove NC GPIO_138 and GPIO_139 setting to fix EMR function
Done
Done
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35881 )
Change subject: mb/google/octopus/variants/fleex: Update GPIOs to fix EMR ......................................................................
Patch Set 3: Code-Review+2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35881 )
Change subject: mb/google/octopus/variants/fleex: Update GPIOs to fix EMR ......................................................................
Patch Set 3: Code-Review+1
Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35881 )
Change subject: mb/google/octopus/variants/fleex: Update GPIOs to fix EMR ......................................................................
mb/google/octopus/variants/fleex: Update GPIOs to fix EMR
Update GPIO_138 and GPIO_139 setting to fix EMR function.
BUG=b:141729962,b:141281846 BRANCH=octopus TEST=verify EMR function in Grob360S.
Change-Id: I28cef592374fb4aeee2f3d3010cc0e237d62a2fd Signed-off-by: John Su john_su@compal.corp-partner.google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/35881 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Marco Chen marcochen@google.com Reviewed-by: EricR Lai ericr_lai@compal.corp-partner.google.com Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net --- M src/mainboard/google/octopus/variants/fleex/gpio.c 1 file changed, 0 insertions(+), 4 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Marco Chen: Looks good to me, approved EricR Lai: Looks good to me, approved
diff --git a/src/mainboard/google/octopus/variants/fleex/gpio.c b/src/mainboard/google/octopus/variants/fleex/gpio.c index a1e02d2..5924fa0 100644 --- a/src/mainboard/google/octopus/variants/fleex/gpio.c +++ b/src/mainboard/google/octopus/variants/fleex/gpio.c @@ -26,10 +26,6 @@ PAD_NC(GPIO_67, UP_20K), PAD_NC(GPIO_117, UP_20K),
- PAD_NC(GPIO_138, UP_20K), - PAD_NC(GPIO_139, UP_20K), - /* GPIO_140 -- PEN_RESET */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_140, 0, DEEP, NONE, Tx1RxDCRx0, DISPUPD), PAD_NC(GPIO_143, UP_20K), PAD_NC(GPIO_144, UP_20K), PAD_NC(GPIO_145, UP_20K),
-
EricR Lai (Code Review) -
Furquan Shaikh (Code Review)
-
John Su (Code Review)
-
Marco Chen (Code Review)
-
Paul Menzel (Code Review)