[M] Change in coreboot[main]: soc/common/smbus: Support reading SPD5 hubs for DDR5

[Tim Crawford (Code Review)]

Attention is currently required from: Angel Pons, Balaji Manigandan, Balaji Manigandan, Haribalaraman Ramasubramanian, Jeremy Soller, Kapil Porwal, Karthik Ramasubramanian, Kyösti Mälkki, Maulik Vaghela, Meera Ravindranath, Nick Vaccaro, Patrick Rudolph, Raj Astekar, Reka Norman, Rizwan Qureshi, Subrata Banik, Tarun Tuli, Tim Crawford, Tim Wawrzynczak.

Tim Crawford has uploaded a new patch set (#16) to the change originally created by Meera Ravindranath. ( https://review.coreboot.org/c/coreboot/+/52731?usp=email )

The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)

Change subject: soc/common/smbus: Support reading SPD5 hubs for DDR5
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soc/common/smbus: Support reading SPD5 hubs for DDR5

DDR5 uses a Serial Presence Detect (SPD) with hub function
(SPD5 hub device) to store the SPD data. The SPD5 hub has 1024 bytes of
EEPROM (`CONFIG_DIMM_SPD_SIZE=1024`).

Change-Id: Ic5e6c58f255bef86b68ce90a4f853bf4e7c7ccfe
Co-authored-by: Meera Ravindranath 
Signed-off-by: Jeremy Soller 
Signed-off-by: Tim Crawford 
---
M src/include/spd_bin.h
M src/lib/spd_cache.c
M src/soc/intel/common/block/smbus/smbuslib.c
3 files changed, 95 insertions(+), 14 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/52731/16