Change in coreboot[master]: nb/intel/sandybridge: add and use defines for ME base and mask registers
Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37970 )
Change subject: nb/intel/sandybridge: add and use defines for ME base and mask registers ......................................................................
nb/intel/sandybridge: add and use defines for ME base and mask registers
TIMELESS_BUILD=1 results in an identical image for X230.
Change-Id: Ia2bd26b97cb2ae77f29d8978f62d2f6be12b43e1 Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/northbridge/intel/sandybridge/finalize.c M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/sandybridge.h 3 files changed, 16 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/37970/1
diff --git a/src/northbridge/intel/sandybridge/finalize.c b/src/northbridge/intel/sandybridge/finalize.c index 50fc755..fc970ba 100644 --- a/src/northbridge/intel/sandybridge/finalize.c +++ b/src/northbridge/intel/sandybridge/finalize.c @@ -24,7 +24,7 @@ pci_or_config16(PCI_DEV_SNB, GGC, 1 << 0); pci_or_config16(PCI_DEV_SNB, PAVPC, 1 << 2); pci_or_config32(PCI_DEV_SNB, DPR, 1 << 0); - pci_or_config32(PCI_DEV_SNB, 0x78, 1 << 10); /* ME */ + pci_or_config32(PCI_DEV_SNB, MEMASK, 1 << 10); pci_or_config32(PCI_DEV_SNB, REMAPBASE, 1 << 0); pci_or_config32(PCI_DEV_SNB, REMAPLIMIT, 1 << 0); pci_or_config32(PCI_DEV_SNB, TOM, 1 << 0); diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 2a52157..8f58dcb 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -585,34 +585,34 @@ pci_write_config32(PCI_DEV(0, 0, 0), BGSM, reg);
if (me_uma_size) { - reg = pci_read_config32(PCI_DEV(0, 0, 0), 0x7c); + reg = pci_read_config32(PCI_DEV(0, 0, 0), MEMASK + 4); val = (0x80000 - me_uma_size) & 0xfffff000; reg = (reg & ~0x000fffff) | (val >> 12); - printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0x7c, reg); - pci_write_config32(PCI_DEV(0, 0, 0), 0x7c, reg); + printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MEMASK + 4, reg); + pci_write_config32(PCI_DEV(0, 0, 0), MEMASK + 4, reg);
// ME base - reg = pci_read_config32(PCI_DEV(0, 0, 0), 0x70); + reg = pci_read_config32(PCI_DEV(0, 0, 0), MEBASE); val = mestolenbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); - printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0x70, reg); - pci_write_config32(PCI_DEV(0, 0, 0), 0x70, reg); + printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MEBASE, reg); + pci_write_config32(PCI_DEV(0, 0, 0), MEBASE, reg);
- reg = pci_read_config32(PCI_DEV(0, 0, 0), 0x74); + reg = pci_read_config32(PCI_DEV(0, 0, 0), MEBASE + 4); val = mestolenbase & 0xfffff000; reg = (reg & ~0x000fffff) | (val >> 12); - printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0x74, reg); - pci_write_config32(PCI_DEV(0, 0, 0), 0x74, reg); + printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MEBASE + 4, reg); + pci_write_config32(PCI_DEV(0, 0, 0), MEBASE + 4, reg);
// ME mask - reg = pci_read_config32(PCI_DEV(0, 0, 0), 0x78); + reg = pci_read_config32(PCI_DEV(0, 0, 0), MEMASK); val = (0x80000 - me_uma_size) & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); reg = (reg & ~0x400) | (1 << 10); // set lockbit on ME mem
reg = (reg & ~0x800) | (1 << 11); // set ME memory enable - printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0x78, reg); - pci_write_config32(PCI_DEV(0, 0, 0), 0x78, reg); + printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MEMASK, reg); + pci_write_config32(PCI_DEV(0, 0, 0), MEMASK, reg); } }
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 54fa66f..6bfe88b 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -82,6 +82,9 @@ #define PAVPC 0x58 /* Protected Audio Video Path Control */ #define DPR 0x5c /* DMA Protected Range */
+#define MEBASE 0x70 +#define MEMASK 0x78 + #define PAM0 0x80 #define PAM1 0x81 #define PAM2 0x82
Hello Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37970
to look at the new patch set (#2).
Change subject: nb/intel/sandybridge: add and use defines for ME base and mask registers ......................................................................
nb/intel/sandybridge: add and use defines for ME base and mask registers
BUILD_TIMELESS=1 results in an identical image for X230.
Change-Id: Ia2bd26b97cb2ae77f29d8978f62d2f6be12b43e1 Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/northbridge/intel/sandybridge/finalize.c M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/sandybridge.h 3 files changed, 16 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/37970/2
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37970
to look at the new patch set (#3).
Change subject: nb/intel/sandybridge: add and use defines for ME base and mask registers ......................................................................
nb/intel/sandybridge: add and use defines for ME base and mask registers
Timeless build results in identical image for X230.
Change-Id: Ia2bd26b97cb2ae77f29d8978f62d2f6be12b43e1 Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/northbridge/intel/sandybridge/finalize.c M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/sandybridge.h 3 files changed, 16 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/37970/3
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37970 )
Change subject: nb/intel/sandybridge: add and use defines for ME base and mask registers ......................................................................
Patch Set 3: Code-Review+2
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37970 )
Change subject: nb/intel/sandybridge: add and use defines for ME base and mask registers ......................................................................
nb/intel/sandybridge: add and use defines for ME base and mask registers
Timeless build results in identical image for X230.
Change-Id: Ia2bd26b97cb2ae77f29d8978f62d2f6be12b43e1 Signed-off-by: Felix Held felix-coreboot@felixheld.de Reviewed-on: https://review.coreboot.org/c/coreboot/+/37970 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Patrick Rudolph siro@das-labor.org --- M src/northbridge/intel/sandybridge/finalize.c M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/sandybridge.h 3 files changed, 16 insertions(+), 13 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved
diff --git a/src/northbridge/intel/sandybridge/finalize.c b/src/northbridge/intel/sandybridge/finalize.c index 50fc755..fc970ba 100644 --- a/src/northbridge/intel/sandybridge/finalize.c +++ b/src/northbridge/intel/sandybridge/finalize.c @@ -24,7 +24,7 @@ pci_or_config16(PCI_DEV_SNB, GGC, 1 << 0); pci_or_config16(PCI_DEV_SNB, PAVPC, 1 << 2); pci_or_config32(PCI_DEV_SNB, DPR, 1 << 0); - pci_or_config32(PCI_DEV_SNB, 0x78, 1 << 10); /* ME */ + pci_or_config32(PCI_DEV_SNB, MEMASK, 1 << 10); pci_or_config32(PCI_DEV_SNB, REMAPBASE, 1 << 0); pci_or_config32(PCI_DEV_SNB, REMAPLIMIT, 1 << 0); pci_or_config32(PCI_DEV_SNB, TOM, 1 << 0); diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 2a52157..8f58dcb 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -585,34 +585,34 @@ pci_write_config32(PCI_DEV(0, 0, 0), BGSM, reg);
if (me_uma_size) { - reg = pci_read_config32(PCI_DEV(0, 0, 0), 0x7c); + reg = pci_read_config32(PCI_DEV(0, 0, 0), MEMASK + 4); val = (0x80000 - me_uma_size) & 0xfffff000; reg = (reg & ~0x000fffff) | (val >> 12); - printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0x7c, reg); - pci_write_config32(PCI_DEV(0, 0, 0), 0x7c, reg); + printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MEMASK + 4, reg); + pci_write_config32(PCI_DEV(0, 0, 0), MEMASK + 4, reg);
// ME base - reg = pci_read_config32(PCI_DEV(0, 0, 0), 0x70); + reg = pci_read_config32(PCI_DEV(0, 0, 0), MEBASE); val = mestolenbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); - printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0x70, reg); - pci_write_config32(PCI_DEV(0, 0, 0), 0x70, reg); + printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MEBASE, reg); + pci_write_config32(PCI_DEV(0, 0, 0), MEBASE, reg);
- reg = pci_read_config32(PCI_DEV(0, 0, 0), 0x74); + reg = pci_read_config32(PCI_DEV(0, 0, 0), MEBASE + 4); val = mestolenbase & 0xfffff000; reg = (reg & ~0x000fffff) | (val >> 12); - printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0x74, reg); - pci_write_config32(PCI_DEV(0, 0, 0), 0x74, reg); + printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MEBASE + 4, reg); + pci_write_config32(PCI_DEV(0, 0, 0), MEBASE + 4, reg);
// ME mask - reg = pci_read_config32(PCI_DEV(0, 0, 0), 0x78); + reg = pci_read_config32(PCI_DEV(0, 0, 0), MEMASK); val = (0x80000 - me_uma_size) & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); reg = (reg & ~0x400) | (1 << 10); // set lockbit on ME mem
reg = (reg & ~0x800) | (1 << 11); // set ME memory enable - printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0x78, reg); - pci_write_config32(PCI_DEV(0, 0, 0), 0x78, reg); + printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MEMASK, reg); + pci_write_config32(PCI_DEV(0, 0, 0), MEMASK, reg); } }
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 54fa66f..6bfe88b 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -82,6 +82,9 @@ #define PAVPC 0x58 /* Protected Audio Video Path Control */ #define DPR 0x5c /* DMA Protected Range */
+#define MEBASE 0x70 +#define MEMASK 0x78 + #define PAM0 0x80 #define PAM1 0x81 #define PAM2 0x82
-
Felix Held (Code Review) -
Patrick Rudolph (Code Review)