Patch set updated for coreboot: nb/i945: Adapt udelay implementation for Netburst CPUs

[Arthur Heymans]

Arthur Heymans ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17831

-gerrit

commit 68ce0715edb4c16c882c413c2c1280c17cefde35
Author: Arthur Heymans 
Date:   Tue Dec 13 11:03:40 2016 +0100

nb/i945: Adapt udelay implementation for Netburst CPUs

Netburst CPUs like the Intel Pentium 4 use msr 0x2c to provide
    info about the FSB frequency.

Change-Id: Iec51cf5c03d49da01630478d7a5fb67aa2440ffd
    Signed-off-by: Arthur Heymans 
---
 src/northbridge/intel/i945/udelay.c | 57 ++++++++++++++++++++++---------------
 1 file changed, 34 insertions(+), 23 deletions(-)

diff --git a/src/northbridge/intel/i945/udelay.c b/src/northbridge/intel/i945/udelay.c
index 27e616b..145d814 100644
--- a/src/northbridge/intel/i945/udelay.c
+++ b/src/northbridge/intel/i945/udelay.c
@@ -18,6 +18,7 @@
 #include <cpu/x86/tsc.h>
 #include <cpu/x86/msr.h>
 #include <cpu/intel/speedstep.h>
+#include <arch/cpu.h>

/**
  * Intel Core(tm) CPUs always run the TSC at the maximum possible CPU clock
@@ -28,32 +29,42 @@ void udelay(u32 us)
    u32 dword;
    tsc_t tsc, tsc1, tscd;
    msr_t msr;
+	u8 fsbcfg;
    u32 fsb = 0, divisor;
    u32 d;			/* ticks per us */

-	msr = rdmsr(MSR_FSB_FREQ);
-	switch (msr.lo & 0x07) {
-	case 5:
-		fsb = 400;
-		break;
-	case 1:
-		fsb = 533;
-		break;
-	case 3:
-		fsb = 667;
-		break;
-	case 2:
-		fsb = 800;
-		break;
-	case 0:
-		fsb = 1067;
-		break;
-	case 4:
-		fsb = 1333;
-		break;
-	case 6:
-		fsb = 1600;
-		break;
+	const u32 eax = cpuid_ext(0x01, 0).eax;
+
+	/* Netburst CPU, model 3,4 or 6 */
+	if (((eax >> 8) & 0xf) == 0xf) {
+		msr = rdmsr(0x2c);
+		fsbcfg = (msr.lo >> 16) & 0x7;
+	} else { /* Intel core or newer */
+		msr = rdmsr(MSR_FSB_FREQ);
+		fsbcfg = (msr.lo & 0x7);
+	}
+	switch (fsbcfg) {
+		case 5:
+			fsb = 400;
+			break;
+		case 1:
+			fsb = 533;
+			break;
+		case 3:
+			fsb = 667;
+			break;
+		case 2:
+			fsb = 800;
+			break;
+		case 0:
+			fsb = 1067;
+			break;
+		case 4:
+			fsb = 1333;
+			break;
+		case 6:
+			fsb = 1600;
+			break;
    }

msr = rdmsr(0x198);