[L] Change in coreboot[master]: mb/inventec: Add Intel SPR server board Inventec Transformers

[Annie Chen (Code Review)]

Attention is currently required from: Angel Pons, Arthur Heymans, David Hendricks, Felix Singer, Hung-Wei Chen, Jonathan Zhang, Lean Sheng Tan, Paul Menzel.

Annie Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75598?usp=email )

Change subject: mb/inventec: Add Intel SPR server board Inventec Transformers
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Patch Set 9:

(6 comments)

File src/mainboard/inventec/transformers/Kconfig:

https://review.coreboot.org/c/coreboot/+/75598/comment/ead0d39f_6b0d0d8c :
PS8, Line 24: 	string
> Please remove, no need to to redefine the type

@

File src/mainboard/inventec/transformers/bootblock.c:

https://review.coreboot.org/c/coreboot/+/75598/comment/404083a0_6e8e3b91 :
PS5, Line 23: 	 * For ArcherCity CRB, only SUART1 is used.
> This seems copy-pasted.

@Paul Menzel This part is same as the AecherCity.

File src/mainboard/inventec/transformers/romstage.c:

https://review.coreboot.org/c/coreboot/+/75598/comment/b08275f0_086e06f2 :
PS5, Line 16: void mainboard_ewl_check(void)
> What is ewl? Please add a comment to the function.

Done

https://review.coreboot.org/c/coreboot/+/75598/comment/74270879_22bc34da :
PS5, Line 102: 	    selftest result first */
> Please align the line correctly.

Done

https://review.coreboot.org/c/coreboot/+/75598/comment/8eb263c8_89007058 :
PS5, Line 118: /* Enable - Portions of memory reference code will be skipped */
             : 	/* when possible to increase boot speed on warm boots.*/
             : 	/* Disable - Disables this feature. */
             : 	/* Auto - Sets it to the MRC default setting. */
> Please use the multi-line commenting style listed in the coding style.

Done

https://review.coreboot.org/c/coreboot/+/75598/comment/ad584745_1f80c936 :
PS5, Line 142: 	/* Disable FSP memory train results*/
> Please add a space at the end.

Done