Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35752 )
Change subject: mb/*/{ms2290,x201}: Complete devicetree ......................................................................
mb/*/{ms2290,x201}: Complete devicetree
This will add the southbridge_intel_ibexpeak chip operations to those PCI devices, making it easier to disable them based on the devicetree content.
Change-Id: Ia6ba4022b0fe4cab70964fbc08d4e9c3b4fde311 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/lenovo/x201/devicetree.cb M src/mainboard/packardbell/ms2290/devicetree.cb 2 files changed, 30 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/35752/1
diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index de6d568..d7d4a91 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -74,9 +74,10 @@
register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
- device pci 16.2 on # IDE/SATA - subsystemid 0x17aa 0x2161 - end + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R, only management boot + device pci 16.3 off end # Management Engine KT
device pci 19.0 on # Ethernet subsystemid 0x17aa 0x2153 @@ -92,14 +93,19 @@
device pci 1c.0 on end # PCIe Port #1 device pci 1c.1 on end # PCIe Port #2 (wwan) + device pci 1c.2 off end device pci 1c.3 on smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end # PCIe Port #4 (Expresscard) device pci 1c.4 on end # PCIe Port #5 (wlan) + device pci 1c.5 off end + device pci 1c.6 off end + device pci 1c.7 off end
device pci 1d.0 on # USB2 EHCI subsystemid 0x17aa 0x2163 end + device pci 1e.0 on end # P2P bridge device pci 1f.0 on # PCI-LPC bridge subsystemid 0x17aa 0x2166 chip superio/nsc/pc87382 @@ -179,6 +185,9 @@ device i2c 5f on end end end + device pci 1f.4 off end + device pci 1f.5 off end + device pci 1f.6 on end end end end diff --git a/src/mainboard/packardbell/ms2290/devicetree.cb b/src/mainboard/packardbell/ms2290/devicetree.cb index c98f9a3..3c912aa 100644 --- a/src/mainboard/packardbell/ms2290/devicetree.cb +++ b/src/mainboard/packardbell/ms2290/devicetree.cb @@ -66,6 +66,13 @@ register "alt_gp_smi_en" = "0x0000" register "gen1_dec" = "0x040069"
+ device pci 16.0 off end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R, only management boot + device pci 16.3 off end # Management Engine KT + + device pci 19.0 off end # Ethernet + device pci 1a.0 on # USB2 EHCI subsystemid 0x1025 0x0379 end @@ -75,11 +82,18 @@ end
device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2 + device pci 1c.2 off end + device pci 1c.3 off end + device pci 1c.4 off end + device pci 1c.5 off end + device pci 1c.6 off end + device pci 1c.7 off end
device pci 1d.0 on # USB2 EHCI subsystemid 0x1025 0x0379 end + device pci 1e.0 on end device pci 1f.0 on # PCI-LPC bridge subsystemid 0x1025 0x0379 end @@ -89,6 +103,9 @@ device pci 1f.3 on # SMBUS subsystemid 0x1025 0x0379 end + device pci 1f.4 off end + device pci 1f.5 off end + device pci 1f.6 off end end end end
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35752 )
Change subject: mb/*/{ms2290,x201}: Complete devicetree ......................................................................
Patch Set 1: Code-Review+1
(1 comment)
See CB:35086 comments?
https://review.coreboot.org/c/coreboot/+/35752/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35752/1//COMMIT_MSG@11 PS1, Line 11: content. Those ops are added in next patch?
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35752 )
Change subject: mb/*/{ms2290,x201}: Complete devicetree ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35752/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35752/1//COMMIT_MSG@11 PS1, Line 11: content.
Those ops are added in next patch?
yes, 35753 adds those ops and 35440 makes them useful by removing the romstage Function Disable write. Should I squash this and 35753?
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35752 )
Change subject: mb/*/{ms2290,x201}: Complete devicetree ......................................................................
Patch Set 1: Code-Review+1
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35752 )
Change subject: mb/*/{ms2290,x201}: Complete devicetree ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35752/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35752/1//COMMIT_MSG@11 PS1, Line 11: content.
yes, 35753 adds those ops and 35440 makes them useful by removing the romstage Function Disable writ […]
I think CB:35753 should go in first, but maybe with the commit message you currently have here. Or squash them, no strong opinions here.
Arthur Heymans has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/35752 )
Change subject: mb/*/{ms2290,x201}: Complete devicetree ......................................................................
Abandoned
squashed in 35753
-
Arthur Heymans (Code Review) -
Kyösti Mälkki (Code Review)
-
Paul Menzel (Code Review)