[XS] Change in coreboot[main]: mb/google/brya/var/xol: Modify clkreq to clksrc mapping for NVMe

[SH Kim (Code Review)]

SH Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81230?usp=email )

Change subject: mb/google/brya/var/xol: Modify clkreq to clksrc mapping for NVMe
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mb/google/brya/var/xol: Modify clkreq to clksrc mapping for NVMe

NVMe using clk_src[0] and clk_req[1] mapping to hardware design,
Due to inconsistency between PMC firmware and FSP, we need to set
clk_src to clk_req number, not same as hardware mapping in coreboot.
Then swap correct setting to clk_src=0,clk_req=1 in mFIT.

BUG=b:328318578
TEST=build firmware and veirfy suspend function on NVMe SKU DUT.

Change-Id: I1777310782a0f4417bd1bb21287bec5852be966e
Signed-off-by: Seunghwan Kim 
---
M src/mainboard/google/brya/variants/xol/overridetree.cb
1 file changed, 5 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/81230/1

diff --git a/src/mainboard/google/brya/variants/xol/overridetree.cb b/src/mainboard/google/brya/variants/xol/overridetree.cb
index b825ddd..80d15fe 100644
--- a/src/mainboard/google/brya/variants/xol/overridetree.cb
+++ b/src/mainboard/google/brya/variants/xol/overridetree.cb
@@ -268,10 +268,13 @@
    		end
    	end
    	device ref pcie4_0 on
-		# Enable CPU PCIE RP 1 using CLK 0
+			# Enable NVMe SSD using clk_src0 and clk_req1 mapping to hardware
+			# design. Due to inconsistency between PMC firmware and FSP, we need
+			# to set clk_src to clk_req number, not same as hardware mapping in
+			# coreboot. Then swap correct setting clksrc, clkreq in mFIT.
    		register "cpu_pcie_rp[CPU_RP(1)]" = "{
    			.clk_req = 1,
-				.clk_src = 0,
+				.clk_src = 1,
    			.flags = PCIE_RP_LTR | PCIE_RP_AER,
    		}"
    		probe STORAGE STORAGE_NVME