Change in coreboot[master]: nb/intel/x4x: allow to force RAM timings ignoring SPD values

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28200 )

Change subject: nb/intel/x4x: allow to force RAM timings ignoring SPD values
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Patch Set 1:

(4 comments)

https://review.coreboot.org/c/coreboot/+/28200/1/src/northbridge/intel/x4x/K... 
File src/northbridge/intel/x4x/Kconfig:

https://review.coreboot.org/c/coreboot/+/28200/1/src/northbridge/intel/x4x/K... 
PS1, Line 49: 	bool "Ignore RAM timing values stored in SPD EEPROMs"
This option should be in an "Overclocking" menu

https://review.coreboot.org/c/coreboot/+/28200/1/src/northbridge/intel/x4x/r... 
File src/northbridge/intel/x4x/raminit.c:

https://review.coreboot.org/c/coreboot/+/28200/1/src/northbridge/intel/x4x/r... 
PS1, Line 116: 	if (IS_ENABLED(CONFIG_RAMINIT_FORCE)) {
You'd still want to use a sticky scratchpad register to recover from non-working values.

If hardcoded timings don't work:
- Write a certain value in a sticky scratchpad register to indicate failure.
- Do a FULL reset. Yes, the one that powers off then on; it's the only way to reset DDR2.
- When reaching this part again, check if the scratchpad has the "failure value". If so, use the SPD timings instead of the hardcoded timings.

https://review.coreboot.org/c/coreboot/+/28200/1/src/northbridge/intel/x4x/r... 
PS1, Line 119: "Overriding probed memory timings:"
             : 			"tclk=%d, CAS=%d\n", CONFIG_RAMINIT_FORCE_TCK,
             : 			CONFIG_RAMINIT_FORCE_CL);
Tried printing the values that get decoded from the SPDs?

Also, I'm not sure how this raminit handles the other timings (they need to be adjusted when the tCK is changed).

https://review.coreboot.org/c/coreboot/+/28200/1/src/northbridge/intel/x4x/r... 
PS1, Line 132: if ((s->selected_timings.CAS < 3) || (s->selected_timings.tclk == 0))
You would still want to keep this check in place.