Change in coreboot[master]: nb/intel/sandybridge/mrc: Handle P2P disabling via devicetree
Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36903 )
Change subject: nb/intel/sandybridge/mrc: Handle P2P disabling via devicetree ......................................................................
nb/intel/sandybridge/mrc: Handle P2P disabling via devicetree
Some Sandy Bridge boards disabled the PCI-to-PCI bridge early to avoid probing by the MRC. We can do that for all boards instead, based on the devicetree setting.
Change-Id: Ie64774628fde77db2a379bdba6a921a31e52fa0d Signed-off-by: Nico Huber nico.h@gmx.de --- M src/mainboard/google/butterfly/early_init.c M src/mainboard/google/parrot/early_init.c M src/mainboard/google/stout/early_init.c M src/mainboard/intel/dcp847ske/early_southbridge.c M src/mainboard/kontron/ktqm77/early_init.c M src/mainboard/roda/rv11/early_init.c M src/northbridge/intel/sandybridge/raminit_mrc.c 7 files changed, 13 insertions(+), 43 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/36903/1
diff --git a/src/mainboard/google/butterfly/early_init.c b/src/mainboard/google/butterfly/early_init.c index 19910ba..fba5ee3 100644 --- a/src/mainboard/google/butterfly/early_init.c +++ b/src/mainboard/google/butterfly/early_init.c @@ -68,12 +68,6 @@ DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); - - /* Disable unused devices (board specific) */ - reg32 = RCBA32(FD); - /* Disable PCI bridge so MRC does not probe this bus */ - reg32 |= PCH_DISABLE_P2P; - RCBA32(FD) = reg32; }
const struct southbridge_usb_port mainboard_usb_ports[] = { diff --git a/src/mainboard/google/parrot/early_init.c b/src/mainboard/google/parrot/early_init.c index 7310b01..ba34be9 100644 --- a/src/mainboard/google/parrot/early_init.c +++ b/src/mainboard/google/parrot/early_init.c @@ -67,12 +67,6 @@ DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); - - /* Disable unused devices (board specific) */ - reg32 = RCBA32(FD); - /* Disable PCI bridge so MRC does not probe this bus */ - reg32 |= PCH_DISABLE_P2P; - RCBA32(FD) = reg32; }
void mainboard_fill_pei_data(struct pei_data *pei_data) diff --git a/src/mainboard/google/stout/early_init.c b/src/mainboard/google/stout/early_init.c index 94d4092..37f93c9 100644 --- a/src/mainboard/google/stout/early_init.c +++ b/src/mainboard/google/stout/early_init.c @@ -71,12 +71,6 @@ DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); DIR_ROUTE(D20IR, PIRQD, PIRQE, PIRQF, PIRQG); - - /* Disable unused devices (board specific) */ - reg32 = RCBA32(FD); - /* Disable PCI bridge so MRC does not probe this bus */ - reg32 |= PCH_DISABLE_P2P; - RCBA32(FD) = reg32; }
/* diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c index 34310a0..9cdcd5d 100644 --- a/src/mainboard/intel/dcp847ske/early_southbridge.c +++ b/src/mainboard/intel/dcp847ske/early_southbridge.c @@ -30,9 +30,6 @@
void mainboard_late_rcba_config(void) { - /* Disable devices */ - RCBA32(FD) |= PCH_DISABLE_P2P; - /* Set "mobile" bit in MCH (which makes sense layout-wise). */ /* Note sure if this has any effect at all though. */ MCHBAR32(0x0004) |= 0x00001000; diff --git a/src/mainboard/kontron/ktqm77/early_init.c b/src/mainboard/kontron/ktqm77/early_init.c index 6a483bc..eac19f4 100644 --- a/src/mainboard/kontron/ktqm77/early_init.c +++ b/src/mainboard/kontron/ktqm77/early_init.c @@ -44,17 +44,6 @@ COMA_LPC_EN | COMB_LPC_EN); }
-void mainboard_late_rcba_config(void) -{ - u32 reg32; - - /* Disable unused devices (board specific) */ - reg32 = RCBA32(FD); - /* Disable PCI bridge so MRC does not probe this bus */ - reg32 |= PCH_DISABLE_P2P; - RCBA32(FD) = reg32; -} - void bootblock_mainboard_early_init(void) { int lvds_3v = 0; /* 0 (5V) or 1 (3V3) */ diff --git a/src/mainboard/roda/rv11/early_init.c b/src/mainboard/roda/rv11/early_init.c index f168138..5c5e8d8 100644 --- a/src/mainboard/roda/rv11/early_init.c +++ b/src/mainboard/roda/rv11/early_init.c @@ -16,17 +16,6 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <southbridge/intel/bd82x6x/pch.h>
-void mainboard_late_rcba_config(void) -{ - u32 reg32; - - /* Disable unused devices (board specific) */ - reg32 = RCBA32(FD); - /* Disable PCI bridge so MRC does not probe this bus */ - reg32 |= PCH_DISABLE_P2P; - RCBA32(FD) = reg32; -} - int mainboard_should_reset_usb(int s3resume) { return !s3resume; diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index a8acfbf..5a00d88 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -18,6 +18,7 @@ #include <bootmode.h> #include <cf9_reset.h> #include <string.h> +#include <device/device.h> #include <device/pci_ops.h> #include <arch/cpu.h> #include <cbmem.h> @@ -382,6 +383,16 @@ pei_data->usb3.xhci_streams = cfg->usb3.xhci_streams; }
+void disable_p2p(void) +{ + /* Disable PCI-to-PCI bridge early to prevent probing by MRC. */ + struct device *const p2p = pcidev_on_root(0x1e, 0); + if (p2p && p2p->enabled) + return; + + RCBA32(FD) |= PCH_DISABLE_P2P; +} + void perform_raminit(int s3resume) { int cbmem_was_initted; @@ -423,6 +434,8 @@ } }
+ disable_p2p(); + pei_data.boot_mode = s3resume ? 2 : 0; timestamp_add_now(TS_BEFORE_INITRAM); sdram_initialize(&pei_data);
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36903
to look at the new patch set (#2).
Change subject: nb/intel/sandybridge/mrc: Handle P2P disabling via devicetree ......................................................................
nb/intel/sandybridge/mrc: Handle P2P disabling via devicetree
Some Sandy Bridge boards disabled the PCI-to-PCI bridge early to avoid probing by the MRC. We can do that for all boards instead, based on the devicetree setting.
Change-Id: Ie64774628fde77db2a379bdba6a921a31e52fa0d Signed-off-by: Nico Huber nico.h@gmx.de --- M src/mainboard/google/butterfly/early_init.c M src/mainboard/google/parrot/early_init.c M src/mainboard/google/stout/early_init.c M src/mainboard/intel/dcp847ske/early_southbridge.c M src/mainboard/kontron/ktqm77/early_init.c M src/mainboard/roda/rv11/early_init.c M src/northbridge/intel/sandybridge/raminit_mrc.c 7 files changed, 13 insertions(+), 43 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/36903/2
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36903 )
Change subject: nb/intel/sandybridge/mrc: Handle P2P disabling via devicetree ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36903/2/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/raminit_mrc.c:
https://review.coreboot.org/c/coreboot/+/36903/2/src/northbridge/intel/sandy... PS2, Line 386: void just static?
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36903
to look at the new patch set (#3).
Change subject: nb/intel/sandybridge/mrc: Handle P2P disabling via devicetree ......................................................................
nb/intel/sandybridge/mrc: Handle P2P disabling via devicetree
Some Sandy Bridge boards disabled the PCI-to-PCI bridge early to avoid probing by the MRC. We can do that for all boards instead, based on the devicetree setting.
Change-Id: Ie64774628fde77db2a379bdba6a921a31e52fa0d Signed-off-by: Nico Huber nico.h@gmx.de --- M src/mainboard/google/butterfly/early_init.c M src/mainboard/google/parrot/early_init.c M src/mainboard/google/stout/early_init.c M src/mainboard/intel/dcp847ske/early_southbridge.c M src/mainboard/kontron/ktqm77/early_init.c M src/mainboard/roda/rv11/early_init.c M src/northbridge/intel/sandybridge/raminit_mrc.c 7 files changed, 13 insertions(+), 43 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/36903/3
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36903
to look at the new patch set (#4).
Change subject: nb/intel/sandybridge/mrc: Handle P2P disabling via devicetree ......................................................................
nb/intel/sandybridge/mrc: Handle P2P disabling via devicetree
Some Sandy Bridge boards disabled the PCI-to-PCI bridge early to avoid probing by the MRC. We can do that for all boards instead, based on the devicetree setting.
Change-Id: Ie64774628fde77db2a379bdba6a921a31e52fa0d Signed-off-by: Nico Huber nico.h@gmx.de --- M src/mainboard/google/butterfly/early_init.c M src/mainboard/google/parrot/early_init.c M src/mainboard/google/stout/early_init.c M src/mainboard/intel/dcp847ske/early_southbridge.c M src/mainboard/kontron/ktqm77/early_init.c M src/mainboard/roda/rv11/early_init.c M src/northbridge/intel/sandybridge/raminit_mrc.c 7 files changed, 13 insertions(+), 49 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/36903/4
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36903 )
Change subject: nb/intel/sandybridge/mrc: Handle P2P disabling via devicetree ......................................................................
Patch Set 4: Code-Review+2
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36903 )
Change subject: nb/intel/sandybridge/mrc: Handle P2P disabling via devicetree ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36903/2/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/raminit_mrc.c:
https://review.coreboot.org/c/coreboot/+/36903/2/src/northbridge/intel/sandy... PS2, Line 386: void
just static?
Done
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36903 )
Change subject: nb/intel/sandybridge/mrc: Handle P2P disabling via devicetree ......................................................................
nb/intel/sandybridge/mrc: Handle P2P disabling via devicetree
Some Sandy Bridge boards disabled the PCI-to-PCI bridge early to avoid probing by the MRC. We can do that for all boards instead, based on the devicetree setting.
Change-Id: Ie64774628fde77db2a379bdba6a921a31e52fa0d Signed-off-by: Nico Huber nico.h@gmx.de Reviewed-on: https://review.coreboot.org/c/coreboot/+/36903 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/google/butterfly/early_init.c M src/mainboard/google/parrot/early_init.c M src/mainboard/google/stout/early_init.c M src/mainboard/intel/dcp847ske/early_southbridge.c M src/mainboard/kontron/ktqm77/early_init.c M src/mainboard/roda/rv11/early_init.c M src/northbridge/intel/sandybridge/raminit_mrc.c 7 files changed, 13 insertions(+), 49 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved
diff --git a/src/mainboard/google/butterfly/early_init.c b/src/mainboard/google/butterfly/early_init.c index 19910ba..4980fa8 100644 --- a/src/mainboard/google/butterfly/early_init.c +++ b/src/mainboard/google/butterfly/early_init.c @@ -30,8 +30,6 @@
void mainboard_late_rcba_config(void) { - u32 reg32; - /* * GFX INTA -> PIRQA (MSI) * D28IP_P1IP WLAN INTA -> PIRQB @@ -68,12 +66,6 @@ DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); - - /* Disable unused devices (board specific) */ - reg32 = RCBA32(FD); - /* Disable PCI bridge so MRC does not probe this bus */ - reg32 |= PCH_DISABLE_P2P; - RCBA32(FD) = reg32; }
const struct southbridge_usb_port mainboard_usb_ports[] = { diff --git a/src/mainboard/google/parrot/early_init.c b/src/mainboard/google/parrot/early_init.c index 7310b01..74c5c86 100644 --- a/src/mainboard/google/parrot/early_init.c +++ b/src/mainboard/google/parrot/early_init.c @@ -28,8 +28,6 @@
void mainboard_late_rcba_config(void) { - u32 reg32; - /* * GFX INTA -> PIRQA (MSI) * D28IP_P2IP WLAN INTA -> PIRQB @@ -67,12 +65,6 @@ DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); - - /* Disable unused devices (board specific) */ - reg32 = RCBA32(FD); - /* Disable PCI bridge so MRC does not probe this bus */ - reg32 |= PCH_DISABLE_P2P; - RCBA32(FD) = reg32; }
void mainboard_fill_pei_data(struct pei_data *pei_data) diff --git a/src/mainboard/google/stout/early_init.c b/src/mainboard/google/stout/early_init.c index 94d4092..754bec6 100644 --- a/src/mainboard/google/stout/early_init.c +++ b/src/mainboard/google/stout/early_init.c @@ -32,8 +32,6 @@
void mainboard_late_rcba_config(void) { - u32 reg32; - /* * GFX INTA -> PIRQA (MSI) * D20IP_XHCI XHCI INTA -> PIRQD (MSI) @@ -71,12 +69,6 @@ DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); DIR_ROUTE(D20IR, PIRQD, PIRQE, PIRQF, PIRQG); - - /* Disable unused devices (board specific) */ - reg32 = RCBA32(FD); - /* Disable PCI bridge so MRC does not probe this bus */ - reg32 |= PCH_DISABLE_P2P; - RCBA32(FD) = reg32; }
/* diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c index 34310a0..9cdcd5d 100644 --- a/src/mainboard/intel/dcp847ske/early_southbridge.c +++ b/src/mainboard/intel/dcp847ske/early_southbridge.c @@ -30,9 +30,6 @@
void mainboard_late_rcba_config(void) { - /* Disable devices */ - RCBA32(FD) |= PCH_DISABLE_P2P; - /* Set "mobile" bit in MCH (which makes sense layout-wise). */ /* Note sure if this has any effect at all though. */ MCHBAR32(0x0004) |= 0x00001000; diff --git a/src/mainboard/kontron/ktqm77/early_init.c b/src/mainboard/kontron/ktqm77/early_init.c index 6a483bc..eac19f4 100644 --- a/src/mainboard/kontron/ktqm77/early_init.c +++ b/src/mainboard/kontron/ktqm77/early_init.c @@ -44,17 +44,6 @@ COMA_LPC_EN | COMB_LPC_EN); }
-void mainboard_late_rcba_config(void) -{ - u32 reg32; - - /* Disable unused devices (board specific) */ - reg32 = RCBA32(FD); - /* Disable PCI bridge so MRC does not probe this bus */ - reg32 |= PCH_DISABLE_P2P; - RCBA32(FD) = reg32; -} - void bootblock_mainboard_early_init(void) { int lvds_3v = 0; /* 0 (5V) or 1 (3V3) */ diff --git a/src/mainboard/roda/rv11/early_init.c b/src/mainboard/roda/rv11/early_init.c index f168138..5c5e8d8 100644 --- a/src/mainboard/roda/rv11/early_init.c +++ b/src/mainboard/roda/rv11/early_init.c @@ -16,17 +16,6 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <southbridge/intel/bd82x6x/pch.h>
-void mainboard_late_rcba_config(void) -{ - u32 reg32; - - /* Disable unused devices (board specific) */ - reg32 = RCBA32(FD); - /* Disable PCI bridge so MRC does not probe this bus */ - reg32 |= PCH_DISABLE_P2P; - RCBA32(FD) = reg32; -} - int mainboard_should_reset_usb(int s3resume) { return !s3resume; diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index a8acfbf..29c766a 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -18,6 +18,7 @@ #include <bootmode.h> #include <cf9_reset.h> #include <string.h> +#include <device/device.h> #include <device/pci_ops.h> #include <arch/cpu.h> #include <cbmem.h> @@ -382,6 +383,16 @@ pei_data->usb3.xhci_streams = cfg->usb3.xhci_streams; }
+static void disable_p2p(void) +{ + /* Disable PCI-to-PCI bridge early to prevent probing by MRC. */ + const struct device *const p2p = pcidev_on_root(0x1e, 0); + if (p2p && p2p->enabled) + return; + + RCBA32(FD) |= PCH_DISABLE_P2P; +} + void perform_raminit(int s3resume) { int cbmem_was_initted; @@ -423,6 +434,8 @@ } }
+ disable_p2p(); + pei_data.boot_mode = s3resume ? 2 : 0; timestamp_add_now(TS_BEFORE_INITRAM); sdram_initialize(&pei_data);
-
Arthur Heymans (Code Review) -
Nico Huber (Code Review)
-
Patrick Georgi (Code Review)