Change in coreboot[master]: soc/intel/alderlake: Add new CPU ID

[Lean Sheng Tan (Code Review)]

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63302 )

Change subject: soc/intel/alderlake: Add new CPU ID
......................................................................

soc/intel/alderlake: Add new CPU ID

Add new CPU ID 0x906A3 (L0 stepping).

Signed-off-by: Lean Sheng Tan 
Change-Id: I280da46e5fdd3792df50556e2804b3bcb346eee3
---
M src/include/cpu/intel/cpu_ids.h
M src/soc/intel/alderlake/bootblock/report_platform.c
M src/soc/intel/common/block/cpu/mp_init.c
3 files changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/63302/1

diff --git a/src/include/cpu/intel/cpu_ids.h b/src/include/cpu/intel/cpu_ids.h
index f0c1baf..6d36851 100644
--- a/src/include/cpu/intel/cpu_ids.h
+++ b/src/include/cpu/intel/cpu_ids.h
@@ -54,6 +54,7 @@
 #define CPUID_ALDERLAKE_J0		0x906a0
 #define CPUID_ALDERLAKE_Q0		0x906a1
 #define CPUID_ALDERLAKE_K0		0x906a2
+#define CPUID_ALDERLAKE_L0		0x906a3
 #define CPUID_ALDERLAKE_R0		0x906a4
 #define CPUID_ALDERLAKE_N_A0		0xb06e0
 #define CPUID_METEORLAKE_A0_1		0xa06a0
diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c
index 721355c..bdce2b7 100644
--- a/src/soc/intel/alderlake/bootblock/report_platform.c
+++ b/src/soc/intel/alderlake/bootblock/report_platform.c
@@ -25,6 +25,7 @@
 } cpu_table[] = {
    { CPUID_ALDERLAKE_J0, "Alderlake J0 Platform" },
    { CPUID_ALDERLAKE_K0, "Alderlake K0 Platform" },
+	{ CPUID_ALDERLAKE_L0, "Alderlake L0 Platform" },
    { CPUID_ALDERLAKE_Q0, "Alderlake Q0 Platform" },
    { CPUID_ALDERLAKE_R0, "Alderlake R0 Platform" },
    { CPUID_ALDERLAKE_N_A0, "Alderlake-N Platform" },
diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c
index 0305815..823f23e 100644
--- a/src/soc/intel/common/block/cpu/mp_init.c
+++ b/src/soc/intel/common/block/cpu/mp_init.c
@@ -72,6 +72,7 @@
    { X86_VENDOR_INTEL, CPUID_ALDERLAKE_S_A0 },
    { X86_VENDOR_INTEL, CPUID_ALDERLAKE_J0 },
    { X86_VENDOR_INTEL, CPUID_ALDERLAKE_K0 },
+	{ X86_VENDOR_INTEL, CPUID_ALDERLAKE_L0 },
    { X86_VENDOR_INTEL, CPUID_ALDERLAKE_Q0 },
    { X86_VENDOR_INTEL, CPUID_ALDERLAKE_R0 },
    { X86_VENDOR_INTEL, CPUID_ALDERLAKE_N_A0 },