Change in coreboot[master]: mb/intel/adlrvp_m: Enable LTR for PCIE - coreboot-gerrit

1 Jun 2021


      Attention is currently required from: Ryan Albazzaz, Paul Menzel.
Bernardo Perez Priego has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54492 )
Change subject: mb/intel/adlrvp_m: Enable LTR for PCIE
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Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/54492/comment/8fbcfd6b_ab7b60f6 
PS1, Line 10: TEST=none
...
It would be nice to check that (`lspci -v`?).
Done
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: If65d08a46b9e7304fbe4b92b7f1e6d4e08c599e7
Gerrit-Change-Number: 54492
Gerrit-PatchSet: 2
Gerrit-Owner: Bernardo Perez Priego bernardo.perez.priego@intel.com
Gerrit-Reviewer: Bora Guvendik bora.guvendik@intel.com
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