Change in coreboot[master]: mainboard/google: Update the TLMM registers for sdhc

[Ravi kumar (Code Review)]

Attention is currently required from: Sajida Bhanu.
Hello Sajida Bhanu,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/57450

to review the following change.

Change subject: mainboard/google: Update the TLMM registers for sdhc
......................................................................

mainboard/google: Update the TLMM registers for sdhc

Update the TLMM register values for eMMC and SD card on Trogdor,
Herobrine and Mistral boards.

BUG=b:196936525
TEST=Validated on qualcomm sc7280 and sc7180 development board and checked
basic boot up.

Signed-off-by: Shaik Sajida Bhanu 
Change-Id: Iccdb7757027c6de424a82e4374bad802501ac83c
---
M src/mainboard/google/herobrine/mainboard.c
M src/mainboard/google/mistral/mainboard.c
M src/mainboard/google/trogdor/mainboard.c
M src/soc/qualcomm/qcs405/include/soc/addressmap.h
M src/soc/qualcomm/sc7180/include/soc/addressmap.h
M src/soc/qualcomm/sc7280/include/soc/addressmap.h
6 files changed, 39 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/57450/1

diff --git a/src/mainboard/google/herobrine/mainboard.c b/src/mainboard/google/herobrine/mainboard.c
index e4ea344..246f710 100644
--- a/src/mainboard/google/herobrine/mainboard.c
+++ b/src/mainboard/google/herobrine/mainboard.c
@@ -12,6 +12,7 @@
 #include <soc/usb/usb_common.h>
 #include <delay.h>
 #include <soc/pcie.h>
+#include <soc/addressmap.h>

static void setup_pcie(void)
 {
@@ -62,12 +63,21 @@
    			GPIO_NO_PULL, GPIO_16MA, GPIO_OUTPUT);
 }

+static void configure_sdhci(void)
+{
+	/*Update TLMM Register for eMMC*/
+	write32((void *)SDC1_TLMM_CFG_ADDR, 0x9FE4);
+	/*Update TLMM Register for SD card*/
+	write32((void *)SDC2_TLMM_CFG_ADDR, 0x1FE4);
+}
+
 static void mainboard_init(struct device *dev)
 {
    /* Configure clock for eMMC */
    clock_configure_sdcc(1, 384 * MHz);
    /* Configure clock for SD card */
    clock_configure_sdcc(2, 50 * MHz);
+	configure_sdhci();

gpi_firmware_load(QUP_0_GSI_BASE);
    gpi_firmware_load(QUP_1_GSI_BASE);
diff --git a/src/mainboard/google/mistral/mainboard.c b/src/mainboard/google/mistral/mainboard.c
index 804afb4..3b5c804 100644
--- a/src/mainboard/google/mistral/mainboard.c
+++ b/src/mainboard/google/mistral/mainboard.c
@@ -3,6 +3,7 @@
 #include <device/device.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 #include <soc/usb.h>
+#include <soc/addressmap.h>

static struct usb_board_data usb1_board_data = {
    .parameter_override_x0 = 0x63,
@@ -17,6 +18,12 @@
    setup_usb_host(HSUSB_HS_PORT_1, &usb1_board_data);
 }

+static void configure_sdhci(void)
+{
+	/*Update TLMM Register for eMMC*/
+	write32((void *)SDC1_TLMM_CFG_ADDR, 0x9FE4);
+}
+
 static void mainboard_init(struct device *dev)
 {
    /* Copy WIFI calibration data into CBMEM. */
@@ -24,6 +31,7 @@
    	cbmem_add_vpd_calibration_data();

setup_usb();
+	configure_sdhci();
 }

static void mainboard_enable(struct device *dev)
diff --git a/src/mainboard/google/trogdor/mainboard.c b/src/mainboard/google/trogdor/mainboard.c
index b55c75f..f68cf2a 100644
--- a/src/mainboard/google/trogdor/mainboard.c
+++ b/src/mainboard/google/trogdor/mainboard.c
@@ -18,6 +18,7 @@
 #include <soc/qcom_qup_se.h>
 #include <soc/usb/usb_common.h>
 #include "board.h"
+#include <soc/addressmap.h>

#define BRIDGE_BUS 0x2
 #define BRIDGE_CHIP 0x2d
@@ -145,6 +146,14 @@
    	fb_new_framebuffer_info_from_edid(&panel->edid, 0);
 }

+static void configure_sdhci(void)
+{
+	/*Update TLMM Register for eMMC*/
+	write32((void *)SDC1_TLMM_CFG_ADDR, 0x9FFF);
+	/*Update TLMM Register for SD card*/
+	write32((void *)SDC2_TLMM_CFG_ADDR, 0x1FE4);
+}
+
 static void mainboard_init(struct device *dev)
 {
    /* Take FPMCU out of reset. Power was already applied
@@ -156,6 +165,7 @@
    qi2s_configure_gpios();
    load_qup_fw();
    display_startup();
+	configure_sdhci();
 }

static void mainboard_enable(struct device *dev)
diff --git a/src/soc/qualcomm/qcs405/include/soc/addressmap.h b/src/soc/qualcomm/qcs405/include/soc/addressmap.h
index b21ae26..6d602eb 100644
--- a/src/soc/qualcomm/qcs405/include/soc/addressmap.h
+++ b/src/soc/qualcomm/qcs405/include/soc/addressmap.h
@@ -9,4 +9,7 @@
 #define TLMM_SOUTH_TILE_BASE		0x1000000
 #define GCC_BASE			0x01800000

+/*SDHC TLMM Registers */
+#define SDC1_TLMM_CFG_ADDR	0x010C2000
+
 #endif /*  __SOC_QUALCOMM_QCS405_ADDRESS_MAP_H__ */
diff --git a/src/soc/qualcomm/sc7180/include/soc/addressmap.h b/src/soc/qualcomm/sc7180/include/soc/addressmap.h
index e360e8a..a2a4461 100644
--- a/src/soc/qualcomm/sc7180/include/soc/addressmap.h
+++ b/src/soc/qualcomm/sc7180/include/soc/addressmap.h
@@ -56,4 +56,8 @@
 #define GPIO_FUNC_QSPI_DATA_1		GPIO65_FUNC_QSPI_DATA_1
 #define GPIO_FUNC_QSPI_CLK		GPIO63_FUNC_QSPI_CLK

+/*SDHC TLMM Registers */
+#define SDC1_TLMM_CFG_ADDR	0x03D7A000
+#define SDC2_TLMM_CFG_ADDR	0x03D7B000
+
 #endif /*  __SOC_QUALCOMM_SC7180_ADDRESS_MAP_H__ */
diff --git a/src/soc/qualcomm/sc7280/include/soc/addressmap.h b/src/soc/qualcomm/sc7280/include/soc/addressmap.h
index b15765f..4f7c398 100644
--- a/src/soc/qualcomm/sc7280/include/soc/addressmap.h
+++ b/src/soc/qualcomm/sc7280/include/soc/addressmap.h
@@ -93,4 +93,8 @@
 /*PHY BCR */
 #define GCC_PCIE_1_PHY_BCR		0x18E01C

+/*SDHC TLMM Registers */
+#define SDC1_TLMM_CFG_ADDR	0x0F1B3000
+#define SDC2_TLMM_CFG_ADDR	0x0F1B4000
+
 #endif /*  __SOC_QUALCOMM_SC7280_ADDRESS_MAP_H__ */