Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37756 )
Change subject: AGESA,binaryPI: Enable lapic early for udelay() ......................................................................
AGESA,binaryPI: Enable lapic early for udelay()
Change-Id: I7200ac0256748d9372fc39be27b86d1c93b38321 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/amd/pi/00630F01/fixme.c M src/cpu/amd/pi/00660F01/fixme.c M src/cpu/amd/pi/00730F01/fixme.c M src/drivers/amd/agesa/bootblock.c 4 files changed, 7 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/37756/1
diff --git a/src/cpu/amd/pi/00630F01/fixme.c b/src/cpu/amd/pi/00630F01/fixme.c index 12f8062..d94215a 100644 --- a/src/cpu/amd/pi/00630F01/fixme.c +++ b/src/cpu/amd/pi/00630F01/fixme.c @@ -85,10 +85,4 @@ LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader); MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); - - if (CONFIG(UDELAY_LAPIC)){ - LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); - MsrReg |= 1 << 11; - LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader); - } } diff --git a/src/cpu/amd/pi/00660F01/fixme.c b/src/cpu/amd/pi/00660F01/fixme.c index 237d52b..7d71e2e 100644 --- a/src/cpu/amd/pi/00660F01/fixme.c +++ b/src/cpu/amd/pi/00660F01/fixme.c @@ -91,10 +91,4 @@ LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader); MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); - - if (CONFIG(UDELAY_LAPIC)) { - LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); - MsrReg |= 1 << 11; - LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader); - } } diff --git a/src/cpu/amd/pi/00730F01/fixme.c b/src/cpu/amd/pi/00730F01/fixme.c index a0621cb..7edd1b8 100644 --- a/src/cpu/amd/pi/00730F01/fixme.c +++ b/src/cpu/amd/pi/00730F01/fixme.c @@ -96,10 +96,4 @@ LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader); MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); - - if (CONFIG(UDELAY_LAPIC)) { - LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); - MsrReg |= 1 << 11; - LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader); - } } diff --git a/src/drivers/amd/agesa/bootblock.c b/src/drivers/amd/agesa/bootblock.c index 9c8bea5..1ed92a2 100644 --- a/src/drivers/amd/agesa/bootblock.c +++ b/src/drivers/amd/agesa/bootblock.c @@ -18,6 +18,7 @@ #include <amdblocks/biosram.h> #include <cpu/amd/msr.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/lapic.h>
#define EARLY_VMTRR_FLASH 6
@@ -60,6 +61,9 @@ enable_pci_mmconf(); set_early_mtrrs();
+ if (CONFIG(UDELAY_LAPIC)) + enable_lapic(); + bootblock_main_with_basetime(base_timestamp); }
@@ -68,6 +72,9 @@ enable_pci_mmconf(); set_early_mtrrs();
+ if (CONFIG(UDELAY_LAPIC)) + enable_lapic(); + void (*ap_romstage_entry)(void) = get_ap_entry_ptr(); ap_romstage_entry(); /* execution does not return */ halt();
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37756 )
Change subject: AGESA,binaryPI: Enable lapic early for udelay() ......................................................................
Patch Set 1: Code-Review+1
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37756 )
Change subject: AGESA,binaryPI: Enable lapic early for udelay() ......................................................................
Patch Set 1: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37756 )
Change subject: AGESA,binaryPI: Enable lapic early for udelay() ......................................................................
Patch Set 1: Code-Review+2
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37756 )
Change subject: AGESA,binaryPI: Enable lapic early for udelay() ......................................................................
Patch Set 1: Code-Review+2
Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37756 )
Change subject: AGESA,binaryPI: Enable lapic early for udelay() ......................................................................
AGESA,binaryPI: Enable lapic early for udelay()
Change-Id: I7200ac0256748d9372fc39be27b86d1c93b38321 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/37756 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Michał Żygowski michal.zygowski@3mdeb.com Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: HAOUAS Elyes ehaouas@noos.fr --- M src/cpu/amd/pi/00630F01/fixme.c M src/cpu/amd/pi/00660F01/fixme.c M src/cpu/amd/pi/00730F01/fixme.c M src/drivers/amd/agesa/bootblock.c 4 files changed, 7 insertions(+), 18 deletions(-)
Approvals: build bot (Jenkins): Verified HAOUAS Elyes: Looks good to me, approved Angel Pons: Looks good to me, approved Michał Żygowski: Looks good to me, approved
diff --git a/src/cpu/amd/pi/00630F01/fixme.c b/src/cpu/amd/pi/00630F01/fixme.c index 12f8062..d94215a 100644 --- a/src/cpu/amd/pi/00630F01/fixme.c +++ b/src/cpu/amd/pi/00630F01/fixme.c @@ -85,10 +85,4 @@ LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader); MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); - - if (CONFIG(UDELAY_LAPIC)){ - LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); - MsrReg |= 1 << 11; - LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader); - } } diff --git a/src/cpu/amd/pi/00660F01/fixme.c b/src/cpu/amd/pi/00660F01/fixme.c index 237d52b..7d71e2e 100644 --- a/src/cpu/amd/pi/00660F01/fixme.c +++ b/src/cpu/amd/pi/00660F01/fixme.c @@ -91,10 +91,4 @@ LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader); MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); - - if (CONFIG(UDELAY_LAPIC)) { - LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); - MsrReg |= 1 << 11; - LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader); - } } diff --git a/src/cpu/amd/pi/00730F01/fixme.c b/src/cpu/amd/pi/00730F01/fixme.c index a0621cb..7edd1b8 100644 --- a/src/cpu/amd/pi/00730F01/fixme.c +++ b/src/cpu/amd/pi/00730F01/fixme.c @@ -96,10 +96,4 @@ LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader); MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); - - if (CONFIG(UDELAY_LAPIC)) { - LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); - MsrReg |= 1 << 11; - LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader); - } } diff --git a/src/drivers/amd/agesa/bootblock.c b/src/drivers/amd/agesa/bootblock.c index 3763b98..91fcc6b 100644 --- a/src/drivers/amd/agesa/bootblock.c +++ b/src/drivers/amd/agesa/bootblock.c @@ -18,6 +18,7 @@ #include <amdblocks/biosram.h> #include <cpu/amd/msr.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/lapic.h>
#define EARLY_VMTRR_FLASH 6
@@ -33,6 +34,9 @@ enable_pci_mmconf(); set_early_mtrrs();
+ if (CONFIG(UDELAY_LAPIC)) + enable_lapic(); + bootblock_main_with_basetime(base_timestamp); }
@@ -41,6 +45,9 @@ enable_pci_mmconf(); set_early_mtrrs();
+ if (CONFIG(UDELAY_LAPIC)) + enable_lapic(); + void (*ap_romstage_entry)(void) = get_ap_entry_ptr(); ap_romstage_entry(); /* execution does not return */ halt();
-
Angel Pons (Code Review) -
HAOUAS Elyes (Code Review)
-
Kyösti Mälkki (Code Review)
-
Michał Żygowski (Code Review)