Jamie Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37874 )
Change subject: soc/intel/cannonlake: Add VR config for CML ......................................................................
soc/intel/cannonlake: Add VR config for CML
Add VR config TdcPowerLimit ,IccMax, DC and AC loadline defaults Add cpu_pl2_4_cfg to switch two kinds of VR design
BUG:b:145094963 BRANCH:none TEST:build coreboot and fsp with enabled fw_debug. Flashed to device and checked the log. All VR configs were set correctly.
Change-Id: I3922bfad5c21dafc64fb05c7d9343b9835b58752 Signed-off-by: Jamie Chen jamie.chen@intel.com --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/include/soc/vr_config.h M src/soc/intel/cannonlake/vr_config.c 3 files changed, 250 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/37874/1
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 85c33db..5b99430 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -218,6 +218,14 @@ uint8_t TcoIrqSelect; uint8_t TcoIrqEnable;
+ /* CPU PL2/4 Config + * Performance: Maximum PLs for maximum performance. + * Baseline: Baseline PLs for balanced performance at lower power. */ + enum { + baseline, + performance + } cpu_pl2_4_cfg; + /* VrConfig Settings for 5 domains * 0 = System Agent, 1 = IA Core, 2 = Ring, * 3 = GT unsliced, 4 = GT sliced */ diff --git a/src/soc/intel/cannonlake/include/soc/vr_config.h b/src/soc/intel/cannonlake/include/soc/vr_config.h index 4cb35a0..8b74cb7 100644 --- a/src/soc/intel/cannonlake/include/soc/vr_config.h +++ b/src/soc/intel/cannonlake/include/soc/vr_config.h @@ -53,9 +53,12 @@ /* AC and DC Loadline in 1/100 mOhms. Range is 0-6249 */ uint16_t ac_loadline; uint16_t dc_loadline; + + uint16_t tdc_powerlimit; };
#define VR_CFG_AMP(i) ((i) * 4) +#define VR_CFG_TDC_AMP(i) ((i) * 8) #define VR_CFG_MOHMS(i) (uint16_t)((i) * 100)
/* VrConfig Settings for 4 domains @@ -85,6 +88,14 @@ [VR_GT_SLICED] = VR_CFG_MOHMS(gt_sl), \ }
+#define VR_CFG_ALL_DOMAINS_TDC(sa, ia, gt_unsl, gt_sl) \ + { \ + [VR_SYSTEM_AGENT] = VR_CFG_TDC_AMP(sa), \ + [VR_IA_CORE] = VR_CFG_TDC_AMP(ia), \ + [VR_GT_UNSLICED] = VR_CFG_TDC_AMP(gt_unsl), \ + [VR_GT_SLICED] = VR_CFG_TDC_AMP(gt_sl), \ + } + void fill_vr_domain_config(void *params, int domain, const struct vr_config *cfg);
diff --git a/src/soc/intel/cannonlake/vr_config.c b/src/soc/intel/cannonlake/vr_config.c index 42c1325..dccc3bd 100644 --- a/src/soc/intel/cannonlake/vr_config.c +++ b/src/soc/intel/cannonlake/vr_config.c @@ -77,6 +77,7 @@ static uint16_t get_sku_icc_max(int domain) { const uint16_t tdp = cpu_get_power_max(); + config_t *cfg = config_of_soc();
static uint16_t mch_id = 0, igd_id = 0; if (!mch_id) { @@ -91,6 +92,7 @@ /* * Iccmax table from Doc #337344 Section 7.2 DC Specifications for CFL. * Iccmax table from Doc #338023 Section 7.2 DC Specifications for WHL. + * Iccmax table from Doc #606599 Section 7.2 DC Specifications for CML. * * Platform Segment SA IA GT (GT/GTx) * --------------------------------------------------------------------- @@ -123,7 +125,30 @@ * WHL-U (15W) GT2 quad 6 70 31 * WHL-U (15W) GT2 dual 6 35 31 * + * CML-U v1/v2 (15W) GT2 hex 6 85(70) 31 + * CML-U v1/v2 (15W) GT2 quad 6 85(70) 31 + * CML-U v1/v2 (15W) GT2 dual 6 35 31 + * + * CML-H (65W) GT2 octa 11.1 192(165) 32 + * CML-H (45W) GT2 octa 11.1 165(140) 32 + * CML-H (45W) GT2 hex 11.1 140(128) 32 + * CML-H (45W) GT2 quad 11.1 105(86) 32 + * + * CML-S (125W)GT2 deca 11.1 245(210) 35 + * CML-S (125W)GT2 octa 11.1 245(210) 35 + * CML-S (125W)GT2 hex 11.1 140 35 + * CML-S XeonW (80W) GT2 deca 11.1 210 35 + * CML-S XeonW (80W) GT2 octa 11.1 210 35 + * CML-S XeonW (80W) GT2 hex 11.1 140 35 + * CML-S (65W) GT2 deca 11.1 210(175) 35 + * CML-S (65W) GT2 octa 11.1 210(175) 35 + * CML-S (65W) GT2 hex 11.1 140 35 + * CML-S (35W) GT2 deca 11.1 140(104) 35 + * CML-S (35W) GT2 octa 11.1 140(104) 35 + * CML-S (35W) GT2 hex 11.1 104 35 + * * GT0 versions are the same as GT2/GT3, but have GT/GTx set to 0. + * () values when PL2_4_Config is baseline. */
if (igd_id == 0xffff && ((domain == VR_GT_SLICED) || (domain == VR_GT_UNSLICED))) @@ -215,6 +240,82 @@
return icc_max[domain]; } + case PCI_DEVICE_ID_INTEL_CML_ULT: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_CML_ULT_6_2: { + uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(6, 85, 31, 31); + if (cfg->cpu_pl2_4_cfg == baseline) + icc_max[VR_IA_CORE] = VR_CFG_AMP(70); + + return icc_max[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_ULT_2_2: { + uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(6, 35, 31, 31); + + return icc_max[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_H_8_2: { + uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 192, 32, 32); + if (tdp >= 65) { /* 65W */ + if (cfg->cpu_pl2_4_cfg == baseline) + icc_max[VR_IA_CORE] = VR_CFG_AMP(165); + else + icc_max[VR_IA_CORE] = VR_CFG_AMP(192); + } else { /* 45W */ + if (cfg->cpu_pl2_4_cfg == baseline) + icc_max[VR_IA_CORE] = VR_CFG_AMP(140); + else + icc_max[VR_IA_CORE] = VR_CFG_AMP(165); + } + return icc_max[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_H: { + uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 140, 32, 32); + + if (cfg->cpu_pl2_4_cfg == baseline) + icc_max[VR_IA_CORE] = VR_CFG_AMP(128); + + return icc_max[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_H_4_2: { + uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 105, 32, 32); + + if (cfg->cpu_pl2_4_cfg == baseline) + icc_max[VR_IA_CORE] = VR_CFG_AMP(86); + + return icc_max[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2: { + uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 140, 35, 35); + if (tdp >= 125) /* 125W */ + if (cfg->cpu_pl2_4_cfg == baseline) + icc_max[VR_IA_CORE] = VR_CFG_AMP(210); + else + icc_max[VR_IA_CORE] = VR_CFG_AMP(245); + else if (tdp >= 80) /* 80W */ + icc_max[VR_IA_CORE] = VR_CFG_AMP(210); + else if (tdp >= 65) /* 65W */ + if (cfg->cpu_pl2_4_cfg == baseline) + icc_max[VR_IA_CORE] = VR_CFG_AMP(175); + else + icc_max[VR_IA_CORE] = VR_CFG_AMP(210); + else /* 35W */ + if (cfg->cpu_pl2_4_cfg == baseline) + icc_max[VR_IA_CORE] = VR_CFG_AMP(104); + else + icc_max[VR_IA_CORE] = VR_CFG_AMP(140); + + return icc_max[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2: { + uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 35, 35); + if (tdp >= 65) /* 125W or 80W or 65W */ + icc_max[VR_IA_CORE] = VR_CFG_AMP(140); + else /* 35W */ + icc_max[VR_IA_CORE] = VR_CFG_AMP(104); + + return icc_max[domain]; + } default: printk(BIOS_ERR, "ERROR: Unknown MCH (0x%x) in VR-config\n", mch_id); } @@ -223,6 +324,7 @@
static uint16_t get_sku_ac_dc_loadline(const int domain) { + const uint16_t tdp = cpu_get_power_max(); static uint16_t mch_id = 0; if (!mch_id) { struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); @@ -271,6 +373,39 @@ VR_CFG_ALL_DOMAINS_LOADLINE(11.1, 2.1, 3.1, 3.1); return loadline[domain]; } + case PCI_DEVICE_ID_INTEL_CML_ULT_2_2: { + const uint16_t loadline[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.4, 3.1, 3.1); + return loadline[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_ULT: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_CML_ULT_6_2: { + const uint16_t loadline[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.8, 3.1, 3.1); + return loadline[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_H_4_2: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_CML_H: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_CML_H_8_2: { + const uint16_t loadline[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.1, 2.7, 2.7); + return loadline[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2: { + uint16_t loadline[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.7, 4.0, 4.0); + if (tdp >= 125) + loadline[VR_IA_CORE] = VR_CFG_MOHMS(1.1); + return loadline[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2: { + uint16_t loadline[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.1, 4.0, 4.0); + if (tdp <= 35) + loadline[VR_IA_CORE] = VR_CFG_MOHMS(1.7); + return loadline[domain]; + } default: printk(BIOS_ERR, "ERROR: Unknown MCH (0x%x) in VR-config\n", mch_id); } @@ -282,6 +417,97 @@ return 1520; }
+static uint16_t get_sku_tdc_powerlimit(int domain) +{ + const uint16_t tdp = cpu_get_power_max(); + config_t *cfg = config_of_soc(); + + static uint16_t mch_id = 0; + if (!mch_id) { + struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); + mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff; + } + + switch (mch_id) { + case PCI_DEVICE_ID_INTEL_CML_ULT: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_CML_ULT_6_2: { + uint16_t tdc[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_TDC(4, 58, 22, 22); + + if (cfg->cpu_pl2_4_cfg == baseline) + tdc[VR_IA_CORE] = VR_CFG_TDC_AMP(48); + + return tdc[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_ULT_2_2: { + const uint16_t tdc[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_TDC(4, 24, 22, 22); + return tdc[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_H_4_2: { + uint16_t tdc[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_TDC(10, 80, 25, 25); + + if (cfg->cpu_pl2_4_cfg == baseline) + tdc[VR_IA_CORE] = VR_CFG_TDC_AMP(60); + + return tdc[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_H: { + uint16_t tdc[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_TDC(10, 92, 25, 25); + + if (cfg->cpu_pl2_4_cfg == baseline) + tdc[VR_IA_CORE] = VR_CFG_TDC_AMP(80); + + return tdc[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_H_8_2: { + uint16_t tdc[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_TDC(10, 125, 25, 25); + + if (tdp >= 65) /* 65W */ + if (cfg->cpu_pl2_4_cfg == baseline) + tdc[VR_IA_CORE] = VR_CFG_TDC_AMP(117); + else + tdc[VR_IA_CORE] = VR_CFG_TDC_AMP(146); + else /* 45W */ + if (cfg->cpu_pl2_4_cfg == baseline) + tdc[VR_IA_CORE] = VR_CFG_TDC_AMP(86); + else + tdc[VR_IA_CORE] = VR_CFG_TDC_AMP(125); + + return tdc[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2: { + uint16_t tdc[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_TDC(10, 74, 28, 28); + + if (tdp >= 125) /* 125W */ + tdc[VR_IA_CORE] = VR_CFG_TDC_AMP(132); + else if (tdp >= 65) /* 80W or 65W */ + tdc[VR_IA_CORE] = VR_CFG_TDC_AMP(104); + else /* 35W */ + tdc[VR_IA_CORE] = VR_CFG_TDC_AMP(74); + + return tdc[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2: + case PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2: { + uint16_t tdc[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_TDC(10, 100, 28, 28); + + if (tdp > 35) /* 125W or 80W or 65W */ + tdc[VR_IA_CORE] = VR_CFG_TDC_AMP(175); + + return tdc[domain]; + } + default: + printk(BIOS_ERR, "ERROR: Unknown MCH (0x%x) in VR-config\n", mch_id); + } + return 0; +} + void fill_vr_domain_config(void *params, int domain, const struct vr_config *chip_cfg) { @@ -326,4 +552,9 @@ vr_params->DcLoadline[domain] = cfg->dc_loadline; else vr_params->DcLoadline[domain] = get_sku_ac_dc_loadline(domain); + + if (cfg->tdc_powerlimit) + vr_params->TdcPowerLimit[domain] = cfg->tdc_powerlimit; + else + vr_params->TdcPowerLimit[domain] = get_sku_tdc_powerlimit(domain); }
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37874 )
Change subject: soc/intel/cannonlake: Add VR config for CML ......................................................................
Patch Set 1:
(3 comments)
https://review.coreboot.org/c/coreboot/+/37874/1/src/soc/intel/cannonlake/vr... File src/soc/intel/cannonlake/vr_config.c:
https://review.coreboot.org/c/coreboot/+/37874/1/src/soc/intel/cannonlake/vr... PS1, Line 283: icc_max[VR_IA_CORE] = VR_CFG_AMP(86); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/37874/1/src/soc/intel/cannonlake/vr... PS1, Line 283: icc_max[VR_IA_CORE] = VR_CFG_AMP(86); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/37874/1/src/soc/intel/cannonlake/vr... PS1, Line 312: if (tdp >= 65) /* 125W or 80W or 65W */ suspect code indent for conditional statements (16, 32)
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37874
to look at the new patch set (#2).
Change subject: soc/intel/cannonlake: Add VR config for CML ......................................................................
soc/intel/cannonlake: Add VR config for CML
Add VR config TdcPowerLimit ,IccMax, DC and AC loadline defaults Add cpu_pl2_4_cfg to switch two kinds of VR design
BUG:b:145094963 BRANCH:none TEST:build coreboot and fsp with enabled fw_debug. Flashed to device and checked the log. All VR configs were set correctly.
Change-Id: I3922bfad5c21dafc64fb05c7d9343b9835b58752 Signed-off-by: Jamie Chen jamie.chen@intel.com --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/include/soc/vr_config.h M src/soc/intel/cannonlake/vr_config.c 3 files changed, 250 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/37874/2
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37874
to look at the new patch set (#3).
Change subject: soc/intel/cannonlake: Add VR config for CML ......................................................................
soc/intel/cannonlake: Add VR config for CML
Add VR config IccMax, DC and AC loadline defaults for CML. Add cpu_pl2_4_cfg to switch two kinds of VR design.
BUG:b:145094963 BRANCH:none TEST:build coreboot and fsp with enabled fw_debug. Flashed to device and checked the log. All VR configs were set correctly.
Change-Id: I3922bfad5c21dafc64fb05c7d9343b9835b58752 Signed-off-by: Jamie Chen jamie.chen@intel.com --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/vr_config.c 2 files changed, 143 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/37874/3
Kane Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37874 )
Change subject: soc/intel/cannonlake: Add VR config for CML ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37874/4/src/soc/intel/cannonlake/ch... File src/soc/intel/cannonlake/chip.h:
https://review.coreboot.org/c/coreboot/+/37874/4/src/soc/intel/cannonlake/ch... PS4, Line 221: /* CPU PL2/4 Config : * Performance: Maximum PLs for maximum performance. : * Baseline: Baseline PLs for balanced performance at lower power. */ pls change the code comment format. /* * CPU PL2/4 Config * Performance: Maximum PLs for maximum performance. * Baseline: Baseline PLs for balanced performance at lower power. */
Kane Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37874 )
Change subject: soc/intel/cannonlake: Add VR config for CML ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37874/4/src/soc/intel/cannonlake/vr... File src/soc/intel/cannonlake/vr_config.c:
https://review.coreboot.org/c/coreboot/+/37874/4/src/soc/intel/cannonlake/vr... PS4, Line 151: () values when PL2_4_Config is baseline. The above values in () are for baseline.
Hello Patrick Rudolph, Kane Chen, Tim Wawrzynczak, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37874
to look at the new patch set (#5).
Change subject: soc/intel/cannonlake: Add VR config for CML ......................................................................
soc/intel/cannonlake: Add VR config for CML
Add VR config IccMax, DC and AC loadline defaults for CML. Add cpu_pl2_4_cfg to switch two kinds of VR design.
BUG:b:145094963 BRANCH:none TEST:build coreboot and fsp with enabled fw_debug. Flashed to device and checked the log. All VR configs were set correctly.
Change-Id: I3922bfad5c21dafc64fb05c7d9343b9835b58752 Signed-off-by: Jamie Chen jamie.chen@intel.com --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/vr_config.c 2 files changed, 144 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/37874/5
Jamie Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37874 )
Change subject: soc/intel/cannonlake: Add VR config for CML ......................................................................
Patch Set 5:
(2 comments)
Patch Set 4:
(1 comment)
How to trigger the build bot to rebuild again?
https://review.coreboot.org/c/coreboot/+/37874/4/src/soc/intel/cannonlake/ch... File src/soc/intel/cannonlake/chip.h:
https://review.coreboot.org/c/coreboot/+/37874/4/src/soc/intel/cannonlake/ch... PS4, Line 221: /* CPU PL2/4 Config : * Performance: Maximum PLs for maximum performance. : * Baseline: Baseline PLs for balanced performance at lower power. */
pls change the code comment format. […]
Done
https://review.coreboot.org/c/coreboot/+/37874/4/src/soc/intel/cannonlake/vr... File src/soc/intel/cannonlake/vr_config.c:
https://review.coreboot.org/c/coreboot/+/37874/4/src/soc/intel/cannonlake/vr... PS4, Line 151: () values when PL2_4_Config is baseline.
The above values in () are for baseline.
Done
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37874 )
Change subject: soc/intel/cannonlake: Add VR config for CML ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/37874/5/src/soc/intel/cannonlake/ch... File src/soc/intel/cannonlake/chip.h:
https://review.coreboot.org/c/coreboot/+/37874/5/src/soc/intel/cannonlake/ch... PS5, Line 226: performance Should performance be the default if cpu_pl2_4_cfg is not explicitly set?
https://review.coreboot.org/c/coreboot/+/37874/5/src/soc/intel/cannonlake/vr... File src/soc/intel/cannonlake/vr_config.c:
https://review.coreboot.org/c/coreboot/+/37874/5/src/soc/intel/cannonlake/vr... PS5, Line 406: VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.1, 4.0, 4.0); : if (tdp <= 35) : loadline[VR_IA_CORE] = VR_CFG_MOHMS(1.7); nit: All the other comparisons in this file are "if (tdp >= ...)". Could you change this one too?
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37874 )
Change subject: soc/intel/cannonlake: Add VR config for CML ......................................................................
Patch Set 5: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/37874/5/src/soc/intel/cannonlake/ch... File src/soc/intel/cannonlake/chip.h:
https://review.coreboot.org/c/coreboot/+/37874/5/src/soc/intel/cannonlake/ch... PS5, Line 226: performance
Should performance be the default if cpu_pl2_4_cfg is not explicitly set?
yes, please commute these two as Tim says.
Hello Patrick Rudolph, Edward O'Callaghan, Kane Chen, Tim Wawrzynczak, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37874
to look at the new patch set (#6).
Change subject: soc/intel/cannonlake: Add VR config for CML ......................................................................
soc/intel/cannonlake: Add VR config for CML
Add VR config IccMax, DC and AC loadline defaults for CML. Add cpu_pl2_4_cfg to switch two kinds of VR design.
BUG:b:145094963 BRANCH:none TEST:build coreboot and fsp with enabled fw_debug. Flashed to device and checked the log. All VR configs were set correctly.
Change-Id: I3922bfad5c21dafc64fb05c7d9343b9835b58752 Signed-off-by: Jamie Chen jamie.chen@intel.com --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/vr_config.c 2 files changed, 144 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/37874/6
Jamie Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37874 )
Change subject: soc/intel/cannonlake: Add VR config for CML ......................................................................
Patch Set 6:
(2 comments)
https://review.coreboot.org/c/coreboot/+/37874/5/src/soc/intel/cannonlake/ch... File src/soc/intel/cannonlake/chip.h:
https://review.coreboot.org/c/coreboot/+/37874/5/src/soc/intel/cannonlake/ch... PS5, Line 226: performance
yes, please commute these two as Tim says.
Done
https://review.coreboot.org/c/coreboot/+/37874/5/src/soc/intel/cannonlake/vr... File src/soc/intel/cannonlake/vr_config.c:
https://review.coreboot.org/c/coreboot/+/37874/5/src/soc/intel/cannonlake/vr... PS5, Line 406: VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.1, 4.0, 4.0); : if (tdp <= 35) : loadline[VR_IA_CORE] = VR_CFG_MOHMS(1.7);
nit: All the other comparisons in this file are "if (tdp >= ...)". […]
Done
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37874 )
Change subject: soc/intel/cannonlake: Add VR config for CML ......................................................................
Patch Set 6: Code-Review+2
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37874 )
Change subject: soc/intel/cannonlake: Add VR config for CML ......................................................................
Patch Set 6: Code-Review+2
Edward Hill has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37874 )
Change subject: soc/intel/cannonlake: Add VR config for CML ......................................................................
Patch Set 6: Code-Review+2
Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37874 )
Change subject: soc/intel/cannonlake: Add VR config for CML ......................................................................
soc/intel/cannonlake: Add VR config for CML
Add VR config IccMax, DC and AC loadline defaults for CML. Add cpu_pl2_4_cfg to switch two kinds of VR design.
BUG:b:145094963 BRANCH:none TEST:build coreboot and fsp with enabled fw_debug. Flashed to device and checked the log. All VR configs were set correctly.
Change-Id: I3922bfad5c21dafc64fb05c7d9343b9835b58752 Signed-off-by: Jamie Chen jamie.chen@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/37874 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Edward O'Callaghan quasisec@chromium.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Reviewed-by: Edward Hill ecgh@chromium.org --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/vr_config.c 2 files changed, 144 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Edward Hill: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved Edward O'Callaghan: Looks good to me, approved
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 85c33db..07a67cd 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -218,6 +218,15 @@ uint8_t TcoIrqSelect; uint8_t TcoIrqEnable;
+ /* CPU PL2/4 Config + * Performance: Maximum PLs for maximum performance. + * Baseline: Baseline PLs for balanced performance at lower power. + */ + enum { + baseline, + performance + } cpu_pl2_4_cfg; + /* VrConfig Settings for 5 domains * 0 = System Agent, 1 = IA Core, 2 = Ring, * 3 = GT unsliced, 4 = GT sliced */ diff --git a/src/soc/intel/cannonlake/vr_config.c b/src/soc/intel/cannonlake/vr_config.c index 7096b62..5fadcf4 100644 --- a/src/soc/intel/cannonlake/vr_config.c +++ b/src/soc/intel/cannonlake/vr_config.c @@ -77,6 +77,7 @@ static uint16_t get_sku_icc_max(int domain) { const uint16_t tdp = cpu_get_power_max(); + config_t *cfg = config_of_soc();
static uint16_t mch_id = 0, igd_id = 0; if (!mch_id) { @@ -91,6 +92,7 @@ /* * Iccmax table from Doc #337344 Section 7.2 DC Specifications for CFL. * Iccmax table from Doc #338023 Section 7.2 DC Specifications for WHL. + * Iccmax table from Doc #606599 Section 7.2 DC Specifications for CML. * * Platform Segment SA IA GT (GT/GTx) * --------------------------------------------------------------------- @@ -123,7 +125,30 @@ * WHL-U (15W) GT2 quad 6 70 31 * WHL-U (15W) GT2 dual 6 35 31 * + * CML-U v1/v2 (15W) GT2 hex 6 85(70) 31 + * CML-U v1/v2 (15W) GT2 quad 6 85(70) 31 + * CML-U v1/v2 (15W) GT2 dual 6 35 31 + * + * CML-H (65W) GT2 octa 11.1 192(165) 32 + * CML-H (45W) GT2 octa 11.1 165(140) 32 + * CML-H (45W) GT2 hex 11.1 140(128) 32 + * CML-H (45W) GT2 quad 11.1 105(86) 32 + * + * CML-S (125W)GT2 deca 11.1 245(210) 35 + * CML-S (125W)GT2 octa 11.1 245(210) 35 + * CML-S (125W)GT2 hex 11.1 140 35 + * CML-S XeonW (80W) GT2 deca 11.1 210 35 + * CML-S XeonW (80W) GT2 octa 11.1 210 35 + * CML-S XeonW (80W) GT2 hex 11.1 140 35 + * CML-S (65W) GT2 deca 11.1 210(175) 35 + * CML-S (65W) GT2 octa 11.1 210(175) 35 + * CML-S (65W) GT2 hex 11.1 140 35 + * CML-S (35W) GT2 deca 11.1 140(104) 35 + * CML-S (35W) GT2 octa 11.1 140(104) 35 + * CML-S (35W) GT2 hex 11.1 104 35 + * * GT0 versions are the same as GT2/GT3, but have GT/GTx set to 0. + * The above values in () are for baseline. */
if (igd_id == 0xffff && ((domain == VR_GT_SLICED) || (domain == VR_GT_UNSLICED))) @@ -215,6 +240,82 @@
return icc_max[domain]; } + case PCI_DEVICE_ID_INTEL_CML_ULT: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_CML_ULT_6_2: { + uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(6, 85, 31, 31); + if (cfg->cpu_pl2_4_cfg == baseline) + icc_max[VR_IA_CORE] = VR_CFG_AMP(70); + + return icc_max[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_ULT_2_2: { + uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(6, 35, 31, 31); + + return icc_max[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_H_8_2: { + uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 192, 32, 32); + if (tdp >= 65) { /* 65W */ + if (cfg->cpu_pl2_4_cfg == baseline) + icc_max[VR_IA_CORE] = VR_CFG_AMP(165); + else + icc_max[VR_IA_CORE] = VR_CFG_AMP(192); + } else { /* 45W */ + if (cfg->cpu_pl2_4_cfg == baseline) + icc_max[VR_IA_CORE] = VR_CFG_AMP(140); + else + icc_max[VR_IA_CORE] = VR_CFG_AMP(165); + } + return icc_max[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_H: { + uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 140, 32, 32); + + if (cfg->cpu_pl2_4_cfg == baseline) + icc_max[VR_IA_CORE] = VR_CFG_AMP(128); + + return icc_max[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_H_4_2: { + uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 105, 32, 32); + + if (cfg->cpu_pl2_4_cfg == baseline) + icc_max[VR_IA_CORE] = VR_CFG_AMP(86); + + return icc_max[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2: { + uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 140, 35, 35); + if (tdp >= 125) /* 125W */ + if (cfg->cpu_pl2_4_cfg == baseline) + icc_max[VR_IA_CORE] = VR_CFG_AMP(210); + else + icc_max[VR_IA_CORE] = VR_CFG_AMP(245); + else if (tdp >= 80) /* 80W */ + icc_max[VR_IA_CORE] = VR_CFG_AMP(210); + else if (tdp >= 65) /* 65W */ + if (cfg->cpu_pl2_4_cfg == baseline) + icc_max[VR_IA_CORE] = VR_CFG_AMP(175); + else + icc_max[VR_IA_CORE] = VR_CFG_AMP(210); + else /* 35W */ + if (cfg->cpu_pl2_4_cfg == baseline) + icc_max[VR_IA_CORE] = VR_CFG_AMP(104); + else + icc_max[VR_IA_CORE] = VR_CFG_AMP(140); + + return icc_max[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2: { + uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 35, 35); + if (tdp >= 65) /* 125W or 80W or 65W */ + icc_max[VR_IA_CORE] = VR_CFG_AMP(140); + else /* 35W */ + icc_max[VR_IA_CORE] = VR_CFG_AMP(104); + + return icc_max[domain]; + } default: printk(BIOS_ERR, "ERROR: Unknown MCH (0x%x) in VR-config\n", mch_id); } @@ -223,6 +324,7 @@
static uint16_t get_sku_ac_dc_loadline(const int domain) { + const uint16_t tdp = cpu_get_power_max(); static uint16_t mch_id = 0; if (!mch_id) { struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); @@ -273,6 +375,39 @@ VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.1, 3.1, 3.1); return loadline[domain]; } + case PCI_DEVICE_ID_INTEL_CML_ULT_2_2: { + const uint16_t loadline[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.4, 3.1, 3.1); + return loadline[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_ULT: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_CML_ULT_6_2: { + const uint16_t loadline[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.8, 3.1, 3.1); + return loadline[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_H_4_2: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_CML_H: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_CML_H_8_2: { + const uint16_t loadline[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.1, 2.7, 2.7); + return loadline[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2: { + uint16_t loadline[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.7, 4.0, 4.0); + if (tdp >= 125) + loadline[VR_IA_CORE] = VR_CFG_MOHMS(1.1); + return loadline[domain]; + } + case PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2: { + uint16_t loadline[NUM_VR_DOMAINS] = + VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.7, 4.0, 4.0); + if (tdp > 35) + loadline[VR_IA_CORE] = VR_CFG_MOHMS(1.1); + return loadline[domain]; + } default: printk(BIOS_ERR, "ERROR: Unknown MCH (0x%x) in VR-config\n", mch_id); }
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