Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48947 )
Change subject: soc/intel/skylake: Add 4 missing root ports ......................................................................
soc/intel/skylake: Add 4 missing root ports
The Kaby Lake PCH can has up to 24 PCIe root ports. Thus, add 4 missing root ports to the chipset devicetree.
Change-Id: I443fb736873d47f1b6fe7718a10e1bb4ae5df2a6 Signed-off-by: Felix Singer felixsinger@posteo.net --- M src/soc/intel/skylake/chipset.cb 1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/48947/1
diff --git a/src/soc/intel/skylake/chipset.cb b/src/soc/intel/skylake/chipset.cb index 136630e..28ee53d 100644 --- a/src/soc/intel/skylake/chipset.cb +++ b/src/soc/intel/skylake/chipset.cb @@ -31,6 +31,10 @@ device pci 1b.1 alias pcie_rp18 off end # PCI Express Port 18 device pci 1b.2 alias pcie_rp19 off end # PCI Express Port 19 device pci 1b.3 alias pcie_rp20 off end # PCI Express Port 20 + device pci 1b.4 alias pcie_rp21 off end # PCI Express Port 21 + device pci 1b.5 alias pcie_rp22 off end # PCI Express Port 22 + device pci 1b.6 alias pcie_rp23 off end # PCI Express Port 23 + device pci 1b.7 alias pcie_rp24 off end # PCI Express Port 24 device pci 1c.0 alias pcie_rp1 off end # PCI Express Port 1 device pci 1c.1 alias pcie_rp2 off end # PCI Express Port 2 device pci 1c.2 alias pcie_rp3 off end # PCI Express Port 3
Hello Nico Huber, Tim Wawrzynczak, Michael Niewöhner, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48947
to look at the new patch set (#2).
Change subject: soc/intel/skylake: Add 4 missing root ports to chipset dt ......................................................................
soc/intel/skylake: Add 4 missing root ports to chipset dt
The Kaby Lake PCH can has up to 24 PCIe root ports. Thus, add 4 missing root ports to the chipset devicetree.
Change-Id: I443fb736873d47f1b6fe7718a10e1bb4ae5df2a6 Signed-off-by: Felix Singer felixsinger@posteo.net --- M src/soc/intel/skylake/chipset.cb 1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/48947/2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48947 )
Change subject: soc/intel/skylake: Add 4 missing root ports to chipset dt ......................................................................
Patch Set 2: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/48947/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/48947/2//COMMIT_MSG@9 PS2, Line 9: can has *can have* or just *has*
Hello build bot (Jenkins), Nico Huber, Paul Menzel, Tim Wawrzynczak, Michael Niewöhner, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48947
to look at the new patch set (#3).
Change subject: soc/intel/skylake: Add 4 missing root ports to chipset dt ......................................................................
soc/intel/skylake: Add 4 missing root ports to chipset dt
The Kaby Lake PCH can have up to 24 PCIe root ports. Thus, add 4 missing root ports to the chipset devicetree.
Change-Id: I443fb736873d47f1b6fe7718a10e1bb4ae5df2a6 Signed-off-by: Felix Singer felixsinger@posteo.net --- M src/soc/intel/skylake/chipset.cb 1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/48947/3
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48947 )
Change subject: soc/intel/skylake: Add 4 missing root ports to chipset dt ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48947/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/48947/2//COMMIT_MSG@9 PS2, Line 9: can has
*can have* or just *has*
Done
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48947 )
Change subject: soc/intel/skylake: Add 4 missing root ports to chipset dt ......................................................................
Patch Set 3: Code-Review+2
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48947 )
Change subject: soc/intel/skylake: Add 4 missing root ports to chipset dt ......................................................................
Patch Set 3: Code-Review+2
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48947 )
Change subject: soc/intel/skylake: Add 4 missing root ports to chipset dt ......................................................................
Patch Set 3: Code-Review+2
Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48947 )
Change subject: soc/intel/skylake: Add 4 missing root ports to chipset dt ......................................................................
soc/intel/skylake: Add 4 missing root ports to chipset dt
The Kaby Lake PCH can have up to 24 PCIe root ports. Thus, add 4 missing root ports to the chipset devicetree.
Change-Id: I443fb736873d47f1b6fe7718a10e1bb4ae5df2a6 Signed-off-by: Felix Singer felixsinger@posteo.net Reviewed-on: https://review.coreboot.org/c/coreboot/+/48947 Reviewed-by: Nico Huber nico.h@gmx.de Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Reviewed-by: Michael Niewöhner foss@mniewoehner.de Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/skylake/chipset.cb 1 file changed, 4 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved Michael Niewöhner: Looks good to me, approved
diff --git a/src/soc/intel/skylake/chipset.cb b/src/soc/intel/skylake/chipset.cb index 136630e..28ee53d 100644 --- a/src/soc/intel/skylake/chipset.cb +++ b/src/soc/intel/skylake/chipset.cb @@ -31,6 +31,10 @@ device pci 1b.1 alias pcie_rp18 off end # PCI Express Port 18 device pci 1b.2 alias pcie_rp19 off end # PCI Express Port 19 device pci 1b.3 alias pcie_rp20 off end # PCI Express Port 20 + device pci 1b.4 alias pcie_rp21 off end # PCI Express Port 21 + device pci 1b.5 alias pcie_rp22 off end # PCI Express Port 22 + device pci 1b.6 alias pcie_rp23 off end # PCI Express Port 23 + device pci 1b.7 alias pcie_rp24 off end # PCI Express Port 24 device pci 1c.0 alias pcie_rp1 off end # PCI Express Port 1 device pci 1c.1 alias pcie_rp2 off end # PCI Express Port 2 device pci 1c.2 alias pcie_rp3 off end # PCI Express Port 3
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Felix Singer (Code Review) -
Michael Niewöhner (Code Review)
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Nico Huber (Code Review)
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Paul Menzel (Code Review)
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Tim Wawrzynczak (Code Review)