[S] Change in coreboot[master]: mb/intel/mtlrvp: Enable GSPI interface for mtlrvp

[Harsha B R (Code Review)]

Attention is currently required from: Jamie Ryu.

Hello Jamie Ryu,

I'd like you to do a code review.
Please visit

https://review.coreboot.org/c/coreboot/+/72706

to review the following change.

Change subject: mb/intel/mtlrvp: Enable GSPI interface for mtlrvp
......................................................................

mb/intel/mtlrvp: Enable GSPI interface for mtlrvp

This patch enables GSPI[1] interface for mtlrvp based on mtlrvp
schematics.

BUG=b:224325352
BRANCH=None
TEST=Able to observe corresponding UPD configuration with FSP dump and
able to boot mtlrvp (LP5/DDR5) to chromeOS.
SPI[0].Mode                 = 0
SPI[0].DefaultCsOutput      = 0
SPI[0].CsMode               = 0
SPI[0].CsState              = 0
SPI[1].Mode                 = 1
SPI[1].DefaultCsOutput      = 0
SPI[1].CsMode               = 0
SPI[1].CsState              = 0

Signed-off-by: Harsha B R 
Change-Id: I3d4c4f19dd80fefa80c365b5ecac0a234f5af860
Signed-off-by: Jamie Ryu 
---
M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
1 file changed, 43 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/72706/1

diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
index 8cdbeea..15c9557 100644
--- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
+++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
@@ -36,6 +36,21 @@
    register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC0)"
    register "tcss_ports[3]" = "TCSS_PORT_DEFAULT(OC0)"

+	register "serial_io_gspi_mode" = "{
+		[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
+		[PchSerialIoIndexGSPI1] = PchSerialIoPci,
+	}"
+
+	register "serial_io_gspi_cs_mode" = "{
+		[PchSerialIoIndexGSPI0] = 0,
+		[PchSerialIoIndexGSPI1] = 0,
+	}"
+
+	register "serial_io_gspi_cs_state" = "{
+		[PchSerialIoIndexGSPI0] = 0,
+		[PchSerialIoIndexGSPI1] = 0,
+	}"
+
    device domain 0 on
    	device ref igpu on end
    	device ref heci1 on end
@@ -71,6 +86,7 @@
    	device ref i2c5 on end
    	device ref shared_sram on end
    	device ref uart0 on end
+		device ref gspi1 on end
    	device ref smbus on end
    end
 end