Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48091 )
Change subject: soc/intel/{skl,cnl}: add NMI_{EN,STS} registers ......................................................................
soc/intel/{skl,cnl}: add NMI_{EN,STS} registers
Add NMI_EN and NMI_STS registers, so they can be configured for using NMI gpios.
References: - CMP-LP: Intel doc# 615146-1.2 - CMP-H: Intel doc# 620855-002 - SPT-H: Intel doc# 332691-003 - SPT-LP: Intel doc# 334659-005 - CNP-H: Intel doc# 337868-002
Test: trigger NMI via gpio on Supermicro X11SSM-F did not work before but now makes the Linux kernel complain about a NMI.
Signed-off-by: Michael Niewöhner foss@mniewoehner.de Change-Id: I4d57ae89423bdaacf84f0bb0282bbb1c9df94598 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48091 Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/cannonlake/gpio.c M src/soc/intel/cannonlake/gpio_cnp_h.c M src/soc/intel/cannonlake/include/soc/gpio_defs.h M src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h M src/soc/intel/skylake/gpio.c M src/soc/intel/skylake/include/soc/gpio_defs.h 6 files changed, 34 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/soc/intel/cannonlake/gpio.c b/src/soc/intel/cannonlake/gpio.c index 3c70ad9..90efacc 100644 --- a/src/soc/intel/cannonlake/gpio.c +++ b/src/soc/intel/cannonlake/gpio.c @@ -76,6 +76,8 @@ .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0, + .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_ABG", .acpi_path = "\_SB.PCI0.GPIO", @@ -96,6 +98,8 @@ .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0, + .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_DFH", .acpi_path = "\_SB.PCI0.GPIO", @@ -116,6 +120,8 @@ .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0, + .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPD", .acpi_path = "\_SB.PCI0.GPIO", @@ -136,6 +142,8 @@ .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0, + .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GP_AC", .acpi_path = "\_SB.PCI0.GPIO", @@ -156,6 +164,8 @@ .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0, + .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_CEJ", .acpi_path = "\_SB.PCI0.GPIO", diff --git a/src/soc/intel/cannonlake/gpio_cnp_h.c b/src/soc/intel/cannonlake/gpio_cnp_h.c index 06e344d..a9035ed 100644 --- a/src/soc/intel/cannonlake/gpio_cnp_h.c +++ b/src/soc/intel/cannonlake/gpio_cnp_h.c @@ -78,6 +78,8 @@ .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0, + .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_AB", .acpi_path = "\_SB.PCI0.GPIO", @@ -98,6 +100,8 @@ .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0, + .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_CDG", .acpi_path = "\_SB.PCI0.GPIO", @@ -118,6 +122,8 @@ .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0, + .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPD", .acpi_path = "\_SB.PCI0.GPIO", @@ -138,6 +144,8 @@ .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0, + .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_KHEF", .acpi_path = "\_SB.PCI0.GPIO", @@ -158,6 +166,8 @@ .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0, + .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_IJ", .acpi_path = "\_SB.PCI0.GPIO", diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_defs.h index e7769b5..c96a67d 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_defs.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_defs.h @@ -236,6 +236,8 @@ #define GPI_INT_EN_0 0x120 #define GPI_SMI_STS_0 0x180 #define GPI_SMI_EN_0 0x1A0 +#define GPI_NMI_STS_0 0x1c0 +#define GPI_NMI_EN_0 0x1e0 #define PAD_CFG_BASE 0x600
#endif diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h b/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h index bd68b04..4f87459 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h @@ -310,6 +310,8 @@ #define GPI_INT_EN_0 0x120 #define GPI_SMI_STS_0 0x180 #define GPI_SMI_EN_0 0x1A0 +#define GPI_NMI_STS_0 0x1c0 +#define GPI_NMI_EN_0 0x1e0 #define PAD_CFG_BASE 0x600
#endif diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c index 5519762..1ac9912 100644 --- a/src/soc/intel/skylake/gpio.c +++ b/src/soc/intel/skylake/gpio.c @@ -62,6 +62,8 @@ .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0, + .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPIO_COM0", .acpi_path = "\_SB.PCI0.GPIO", @@ -84,6 +86,8 @@ .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0, + .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPIO_COM1", .acpi_path = "\_SB.PCI0.GPIO", @@ -107,6 +111,8 @@ .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0, + .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPIO_COM3", .acpi_path = "\_SB.PCI0.GPIO", @@ -125,6 +131,8 @@ .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0, + .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPIO_COM2", .acpi_path = "\_SB.PCI0.GPIO", diff --git a/src/soc/intel/skylake/include/soc/gpio_defs.h b/src/soc/intel/skylake/include/soc/gpio_defs.h index 2a5e788..de14bb6 100644 --- a/src/soc/intel/skylake/include/soc/gpio_defs.h +++ b/src/soc/intel/skylake/include/soc/gpio_defs.h @@ -216,5 +216,7 @@ #define GPI_INT_EN_0 0x120 #define GPI_SMI_STS_0 0x180 #define GPI_SMI_EN_0 0x1a0 +#define GPI_NMI_STS_0 0x1c0 +#define GPI_NMI_EN_0 0x1e0
#endif /* _SOC_GPIO_DEFS_H_ */
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Michael Niewöhner (Code Review)