[M] Change in coreboot[main]: soc/amd/glinda/cpu: Add SMBIOS helper

[Naresh Solanki (Code Review)]

Naresh Solanki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87123?usp=email )

Change subject: soc/amd/glinda/cpu: Add SMBIOS helper
......................................................................

soc/amd/glinda/cpu: Add SMBIOS helper

In Glinda SoC,
1. It has multiple L3 caches block, each identified by a unique cache
UID. Each core is associated with a specific L3 cache, which can be
determined based on the CPU core ID.
2. Each CPU core have slightly different CPU boost frequency.

For L3 cache info in DMI table type 7, the default implementation
(x86_get_cpu_cache_info) retrieves cache information only for the
current core and assumes that the same L3 cache is shared across all
cores.

To accurately determine the total L3 cache size:
1. Retrieves L3 cache information for each CPU core.
2. Identifies the unique cache ID associated with each core.
3. Aggregates cache sizes for all unique cache IDs to compute the
   total L3 cache size, ensuring correct summation even when L3 cache
   blocks have different sizes.

Additionally to get core max boost frequency,
1. Determine max boost frequency among all cores & update
   smbios_cpu_get_max_speed_mhz such that it return max of all cores.

TEST=Build for Glinda SoC & check output of `dmidecode -t 7` &
`dmidecode -t 4`. Verify DMI Type7 table to report L3 cache size as 24MB
(16 + 8) & Also verify DMI Type4 'Max Speed: 5408 MHz' which is maximum
boost clock frequency.

Change-Id: I2569a9c744f7f41e4df692626e77a178184b7e0e
Signed-off-by: Naresh Solanki 
---
M src/soc/amd/glinda/Kconfig
M src/soc/amd/glinda/cpu.c
2 files changed, 56 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/87123/1

diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig
index a02492c..1329108 100644
--- a/src/soc/amd/glinda/Kconfig
+++ b/src/soc/amd/glinda/Kconfig
@@ -81,6 +81,7 @@
    select SOC_AMD_COMMON_FSP_PCI			# TODO: Check if this is still correct
    select SOC_AMD_COMMON_FSP_PRELOAD_FSPS
    select SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP
+	select SOC_FILL_CPU_CACHE_INFO
    select SSE2
    select UDK_2017_BINDING
    select USE_DDR5
diff --git a/src/soc/amd/glinda/cpu.c b/src/soc/amd/glinda/cpu.c
index a716127..b00130c 100644
--- a/src/soc/amd/glinda/cpu.c
+++ b/src/soc/amd/glinda/cpu.c
@@ -4,20 +4,75 @@

#include <amdblocks/cpu.h>
 #include <amdblocks/mca.h>
+#include <cpu/amd/cpuid.h>
 #include <cpu/amd/microcode.h>
 #include <cpu/cpu.h>
 #include <device/device.h>
+#include <smbios.h>
 #include <soc/cpu.h>

_Static_assert(CONFIG_MAX_CPUS == 24, "Do not override MAX_CPUS. To reduce the number of "
    "available cores, use the downcore_mode and disable_smt devicetree settings instead.");

+static struct core_info core_info_list[CONFIG_MAX_CPUS];
+
+unsigned int smbios_cpu_get_max_speed_mhz(void)
+{
+	uint32_t max_freq = 0;
+
+	for (int i = 0; i < get_cpu_count(); i++) {
+		struct core_info *core_info = &core_info_list[i];
+
+		if (max_freq < core_info->max_frequency)
+			max_freq = core_info->max_frequency;
+	}
+	return max_freq;
+}
+
+bool soc_fill_cpu_cache_info(uint8_t level, struct cpu_cache_info *info)
+{
+	if (level != CACHE_L3)
+		return x86_get_cpu_cache_info(level, info);
+
+	if (!info)
+		return false;
+
+	uint32_t total_cache = 0;
+	bool seen_cache_ids[CONFIG_MAX_CPUS] = {false};
+
+	x86_get_cpu_cache_info(level, info);
+
+	/*
+	 * To calculate the total L3 cache size, iterate over core_info_list and add up the sizes
+	 * of the L3 cache blocks with unique cache ID.
+	 */
+	for (int i = 0; i < get_cpu_count(); i++) {
+		struct core_info *cache = &core_info_list[i];
+
+		printk(BIOS_SPEW, "CPU %d: Cache Level: %d, Cache Size: %zu bytes\n",
+		       i, cache->l3_cache_uid, cache->l3_cache_size);
+
+		if (!seen_cache_ids[cache->l3_cache_uid]) {
+			total_cache += cache->l3_cache_size;
+			seen_cache_ids[cache->l3_cache_uid] = true;
+		}
+	}
+
+	info->num_cores_shared = get_cpu_count();
+	info->size = total_cache;
+
+	printk(BIOS_SPEW, "Max cache at level: %d is:%zu\n", level, info->size);
+	return true;
+}
+
 static void zen_2_3_init(struct device *dev)
 {
    check_mca();
    set_cstate_io_addr();

amd_apply_microcode_patch();
+
+	ap_stash_core_info(core_info_list);
 }

static struct device_operations cpu_dev_ops = {