Leroy P Leahy (leroy.p.leahy@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13444
-gerrit
commit 581a88dfeac3d556336b1e2fb404eaead414f4ab Author: Lee Leahy leroy.p.leahy@intel.com Date: Sat Jan 30 17:40:40 2016 -0800
Documentation: x86 Enable Serial Output
Document the steps necessary to enable serial output
TEST=None
Change-Id: Ifc0e700d7ef54fb1e28ca9bca34b94cccd3633ac Signed-off-by: Lee Leahy leroy.p.leahy@intel.com --- Documentation/Intel/Board/board.html | 25 +++++++++++++++++++ Documentation/Intel/SoC/soc.html | 47 +++++++++++++++++++++++++++++++++--- Documentation/Intel/development.html | 11 +++++++++ Documentation/Intel/fsp1_1.html | 14 +++++++++++ 4 files changed, 94 insertions(+), 3 deletions(-)
diff --git a/Documentation/Intel/Board/board.html b/Documentation/Intel/Board/board.html index 71acfff..59aed39 100644 --- a/Documentation/Intel/Board/board.html +++ b/Documentation/Intel/Board/board.html @@ -14,6 +14,7 @@ </p> <ol> <li><a href="#RequiredFiles">Required Files</a></li> + <li>Enable <a href="#SerialOutput">Serial Output</a></li> </ol>
@@ -78,6 +79,30 @@
<hr> +<h1><a name="SerialOutput">Enable Serial Output</a></h1> +<p> + Use the following steps to enable serial output: +</p> +<ol> + <li>Implement the car_mainboard_pre_console_init routine in the com_init.c + file: + <ol type="A"> + <li>Power on and enable the UART controller</li> + <li>Connect the UART receive and transmit data lines to the + appropriate SoC pins + </li> + </ol> + </li> + <li>Add Makefile.inc + <ol type="A"> + <li>Add com_init.c to romstage</li> + </ol> + </li> +</ol> + + + +<hr> <p>Modified: 30 January 2016</p> </body> </html> \ No newline at end of file diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html index 7a74554..700a4a3 100644 --- a/Documentation/Intel/SoC/soc.html +++ b/Documentation/Intel/SoC/soc.html @@ -19,6 +19,11 @@ <li><a href="#EarlyDebug">Early Debug</a></li> <li><a href="#Bootblock">Bootblock</a></li> <li><a href="#TempRamInit">TempRamInit</a></li> + <li><a href="#Romstage">Romstage</a> + <ol type="A"> + <li>Enable <a href="#SerialOutput">Serial Output"</a></li> + </ol> + </li> </ol>
@@ -197,9 +202,6 @@ mv build/coreboot.rom.new build/coreboot.rom
<hr> -<<<<<<< HEAD:Documentation/Intel/SoC/soc.html -<p>Modified: 30 January 2016</p> -======= <h1><a name="TempRamInit">TempRamInit</a></h1> <p> Enable the call to TempRamInit using the following steps: @@ -270,6 +272,45 @@ mv build/coreboot.rom.new build/coreboot.rom
<hr> +<h1><a name="Romstage">Romstage</a></h1> + +<h2><a name="SerialOutput">Serial Output</a></h2> +<p> + The following steps add the serial output support for romstage: +</p> +<ol> + <li>Create the romstage subdirectory</li> + <li>Add romstage/romstage.c + <ol type="A"> + <li>Program the necessary base addresses</li> + <li>Disable the TCO</li> + </ol> + </li> + <li>Add romstage/Makefile.inc + <ol type="A"> + <li>Add romstage.c to romstage</li> + </ol> + </li> + <li>Add gpio configuration support if necessary</li> + <li>Add the necessary .h files to support the build</li> + <li>Update Makefile.inc + <ol type="A"> + <li>Add the romstage subdirectory</li> + <li>Add the gpio configuration support file to romstage</li> + </ol> + </li> + <li>Set the necessary Kconfig values to enable serial output: + <ul> + <li>CONFIG_DRIVERS_UART_<driver>=y</li> + <li>CONFIG_CONSOLE_SERIAL=y</li> + <li>CONFIG_UART_FOR_CONSOLE=<port></li> + <li>CONFIG_CONSOLE_SERIAL_115200=y</li> + </ul> + </li> +</ol> + + +<hr> <p>Modified: 30 January 2016</p> </body> </html> \ No newline at end of file diff --git a/Documentation/Intel/development.html b/Documentation/Intel/development.html index d07bfb6..d1dd3a2 100644 --- a/Documentation/Intel/development.html +++ b/Documentation/Intel/development.html @@ -62,6 +62,17 @@ <li><a target="_blank" href="SoC/soc.html#EarlyDebug">Early Debug</a></li> <li>Implement and debug the <a target="_blank" href="SoC/soc.html#Bootblock">bootblock</a> code</li> <li>Implement and debug the call to <a target="_blank" href="SoC/soc.html#TempRamInit">TempRamInit</a></li> + <li>Enable the serial port + <ol type="A"> + <li>Power on, enable and configure GPIOs for the + <a target="_blank" href="Board/board.html#SerialOutput">debug serial UART</a> + </li> + <li>Add the <a target="_blank" href="SoC/soc.html#SerialOutput">serial outupt</a> + support to romstage + </li> + </ol> + </li> + <li>Enable <a target="_blank" href="fsp1_1.html#CorebootFspDebugging">coreboot/FSP</a> debugging</li> </ol>
diff --git a/Documentation/Intel/fsp1_1.html b/Documentation/Intel/fsp1_1.html index 33385ac..53fc8e0 100644 --- a/Documentation/Intel/fsp1_1.html +++ b/Documentation/Intel/fsp1_1.html @@ -15,6 +15,7 @@ <ol> <li><a href="#RequiredFiles">Required Files</a></li> <li>Add the <a href="#FspBinary">FSP Binary File</a> to the Coreboot File System</li> + <li>Enable <a href="#CorebootFspDebugging">coreboot/FSP Debugging</a></li> </ol>
<p> @@ -58,6 +59,19 @@
<hr> +<h1><a name="CorebootFspDebugging">Enable coreboot/FSP Debugging</a></h1> +<p> + Set the following Kconfig values: +</p> +<ul> + <li>CONFIG_DISPLAY_FSP_ENTRY_POINTS - Display the FSP entry points in romstage</li> + <li>CONFIG_DISPLAY_HOBS - Display and verify the hand-off-blocks (HOBs) returned by MemoryInit</li> + <li>CONFIG_DISPLAY_VBT - Display Video BIOS Table (VBT) used for GOP</li> + <li>CONFIG_DISPLAY_UPD_DATA - Display the user specified product data passed to MemoryInit and SiliconInit</li> +</ul> + + +<hr> <p>Modified: 30 January 2016</p> </body> </html> \ No newline at end of file
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Leroy P Leahy