Erin Lo has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34382 )
Change subject: WIP: mediatek/mt8183: Add SCP work support ......................................................................
WIP: mediatek/mt8183: Add SCP work support
Load SCP firmware to SCP's sram since buffer size is limited so load splitted binaries. After SCP works done, disable it
Test=Build pass
Change-Id: I0801eac078aa9d6237142dcd92a3c3e9237a86ee Signed-off-by: Erin Lo erin.lo@mediatek.com --- M src/mainboard/google/kukui/Makefile.inc M src/mainboard/google/kukui/romstage.c M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/include/soc/addressmap.h A src/soc/mediatek/mt8183/include/soc/scp.h A src/soc/mediatek/mt8183/scp.c 6 files changed, 123 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/34382/1
diff --git a/src/mainboard/google/kukui/Makefile.inc b/src/mainboard/google/kukui/Makefile.inc index a0556c1..f8a5bab 100644 --- a/src/mainboard/google/kukui/Makefile.inc +++ b/src/mainboard/google/kukui/Makefile.inc @@ -25,3 +25,18 @@ ramstage-y += mainboard.c ramstage-y += memlayout.ld ramstage-y += reset.c + +cbfs-files-y += scp_0.bin +scp_0.bin-file := 3rdparty/blobs/mainboard/google/kukui/scp_0.bin +scp_0.bin-type := raw +scp_0.bin-compression := none + +cbfs-files-y += scp_1.bin +scp_1.bin-file := 3rdparty/blobs/mainboard/google/kukui/scp_1.bin +scp_1.bin-type := raw +scp_1.bin-compression := none + +cbfs-files-y += scp_2.bin +scp_2.bin-file := 3rdparty/blobs/mainboard/google/kukui/scp_2.bin +scp_2.bin-type := raw +scp_2.bin-compression := none diff --git a/src/mainboard/google/kukui/romstage.c b/src/mainboard/google/kukui/romstage.c index 1465243..cf3572d 100644 --- a/src/mainboard/google/kukui/romstage.c +++ b/src/mainboard/google/kukui/romstage.c @@ -19,7 +19,7 @@ #include <soc/mt6358.h> #include <soc/pll.h> #include <soc/rtc.h> - +#include <soc/scp.h> #include "early_init.h"
void platform_romstage_main(void) @@ -33,6 +33,7 @@ pmic_set_vsim2_cali(2700); mt_pll_raise_ca53_freq(1989 * MHz); rtc_boot(); + scp_work(); mt_mem_init(get_sdram_config()); mtk_mmu_after_dram(); } diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index d35a07e..0543552 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -35,6 +35,7 @@ romstage-y += ../common/pll.c pll.c romstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6358.c romstage-y += ../common/rtc.c rtc.c +romstage-y += scp.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c romstage-y += ../common/timer.c romstage-y += ../common/uart.c diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h index e9f80d1..affc776 100644 --- a/src/soc/mediatek/mt8183/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h @@ -34,6 +34,9 @@ EMI_BASE = IO_PHYS + 0x00219000, EMI_MPU_BASE = IO_PHYS + 0x00226000, DRAMC_CH_BASE = IO_PHYS + 0x00228000, + SCP_SRAM_BASE = IO_PHYS + 0x00500000, + SCP_CFG_BASE = IO_PHYS + 0x005C0000, + SCP_CLK_CTRL_BASE = IO_PHYS + 0x005C4000, AUXADC_BASE = IO_PHYS + 0x01001000, UART0_BASE = IO_PHYS + 0x01002000, SPI0_BASE = IO_PHYS + 0x0100A000, diff --git a/src/soc/mediatek/mt8183/include/soc/scp.h b/src/soc/mediatek/mt8183/include/soc/scp.h new file mode 100644 index 0000000..a3003bd --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/scp.h @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_MEDIATEK_MT8183_SCP_H +#define SOC_MEDIATEK_MT8183_SCP_H + +#include <soc/addressmap.h> +#include <types.h> + +struct mt8183_scp_regs { + u32 sw_rstn; + u32 reserved[19]; + u32 gpr0; +}; + +struct mt8183_scp_clk_ctrl_regs { + u32 reserved[11]; + u32 sram_pdn; +}; + +static struct mt8183_scp_regs *const mt8183_scp = (void *)SCP_CFG_BASE; +static struct mt8183_scp_clk_ctrl_regs *const mt8183_scp_clk_ctrl = (void *)SCP_CLK_CTRL_BASE; +void scp_work(void); +#endif /* SOC_MEDIATEK_MT8183_SCP_H */ diff --git a/src/soc/mediatek/mt8183/scp.c b/src/soc/mediatek/mt8183/scp.c new file mode 100644 index 0000000..150eeba --- /dev/null +++ b/src/soc/mediatek/mt8183/scp.c @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/barrier.h> +#include <cbfs.h> +#include <console/console.h> +#include <arch/mmio.h> +#include <soc/scp.h> +#include <string.h> + +#define BUF_SIZE (40 * KiB) +static uint8_t scp_bin[BUF_SIZE] __aligned(8); + +void scp_work(void) +{ + size_t fw_size; + + write32(&mt8183_scp_clk_ctrl->sram_pdn, 0x0); + mb(); + + fw_size = cbfs_boot_load_file("scp_0.bin", + scp_bin, + sizeof(scp_bin), + CBFS_TYPE_RAW); + if (fw_size == 0) + die("SCP file :scp_0.bin not found."); + memcpy((void *)SCP_SRAM_BASE + 0x0, scp_bin, fw_size); + + fw_size = cbfs_boot_load_file("scp_1.bin", + scp_bin, + sizeof(scp_bin), + CBFS_TYPE_RAW); + memcpy((void *)SCP_SRAM_BASE + BUF_SIZE, scp_bin, fw_size); + if (fw_size == 0) + die("SCP file :scp_1.bin not found."); + + fw_size = cbfs_boot_load_file("scp_2.bin", + scp_bin, + sizeof(scp_bin), + CBFS_TYPE_RAW); + if (fw_size == 0) + die("SCP file :scp_2.bin not found."); + memcpy((void *)SCP_SRAM_BASE + BUF_SIZE*2, scp_bin, fw_size); + + + /* Memory barrier to ensure that all fw code is loaded + before we release the reset pin. */ + mb(); + write32(&mt8183_scp->sw_rstn, 0x1); + while (read32(&mt8183_scp->gpr0) != 0xaaaa){} + mb(); + write32(&mt8183_scp->sw_rstn, 0x0); + printk(BIOS_DEBUG, "scp finished \n"); +}
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34382 )
Change subject: WIP: mediatek/mt8183: Add SCP work support ......................................................................
Patch Set 1:
(14 comments)
https://review.coreboot.org/c/coreboot/+/34382/1/src/soc/mediatek/mt8183/inc... File src/soc/mediatek/mt8183/include/soc/scp.h:
https://review.coreboot.org/c/coreboot/+/34382/1/src/soc/mediatek/mt8183/inc... PS1, Line 29: u32 reserved[11]; code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/34382/1/src/soc/mediatek/mt8183/inc... PS1, Line 29: u32 reserved[11]; please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34382/1/src/soc/mediatek/mt8183/inc... PS1, Line 30: u32 sram_pdn; code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/34382/1/src/soc/mediatek/mt8183/inc... PS1, Line 30: u32 sram_pdn; please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34382/1/src/soc/mediatek/mt8183/scp... File src/soc/mediatek/mt8183/scp.c:
https://review.coreboot.org/c/coreboot/+/34382/1/src/soc/mediatek/mt8183/scp... PS1, Line 31: mb(); memory barrier without comment
https://review.coreboot.org/c/coreboot/+/34382/1/src/soc/mediatek/mt8183/scp... PS1, Line 45: memcpy((void *)SCP_SRAM_BASE + BUF_SIZE, scp_bin, fw_size); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/34382/1/src/soc/mediatek/mt8183/scp... PS1, Line 45: memcpy((void *)SCP_SRAM_BASE + BUF_SIZE, scp_bin, fw_size); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34382/1/src/soc/mediatek/mt8183/scp... PS1, Line 55: memcpy((void *)SCP_SRAM_BASE + BUF_SIZE*2, scp_bin, fw_size); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/34382/1/src/soc/mediatek/mt8183/scp... PS1, Line 55: memcpy((void *)SCP_SRAM_BASE + BUF_SIZE*2, scp_bin, fw_size); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34382/1/src/soc/mediatek/mt8183/scp... PS1, Line 62: while (read32(&mt8183_scp->gpr0) != 0xaaaa){} space required before the open brace '{'
https://review.coreboot.org/c/coreboot/+/34382/1/src/soc/mediatek/mt8183/scp... PS1, Line 62: while (read32(&mt8183_scp->gpr0) != 0xaaaa){} trailing statements should be on next line
https://review.coreboot.org/c/coreboot/+/34382/1/src/soc/mediatek/mt8183/scp... PS1, Line 62: while (read32(&mt8183_scp->gpr0) != 0xaaaa){} braces {} are not necessary for single statement blocks
https://review.coreboot.org/c/coreboot/+/34382/1/src/soc/mediatek/mt8183/scp... PS1, Line 63: mb(); memory barrier without comment
https://review.coreboot.org/c/coreboot/+/34382/1/src/soc/mediatek/mt8183/scp... PS1, Line 65: printk(BIOS_DEBUG, "scp finished \n"); unnecessary whitespace before a quoted newline
Hello Julius Werner, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34382
to look at the new patch set (#2).
Change subject: WIP: mediatek/mt8183: Add SCP work support ......................................................................
WIP: mediatek/mt8183: Add SCP work support
Load SCP firmware to SCP's sram since buffer size is limited so load splitted binaries. After SCP works done, disable it
Test=Build pass
Change-Id: I0801eac078aa9d6237142dcd92a3c3e9237a86ee Signed-off-by: Erin Lo erin.lo@mediatek.com --- M src/mainboard/google/kukui/Makefile.inc M src/mainboard/google/kukui/romstage.c M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/include/soc/addressmap.h A src/soc/mediatek/mt8183/include/soc/scp.h A src/soc/mediatek/mt8183/scp.c 6 files changed, 130 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/34382/2
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34382 )
Change subject: WIP: mediatek/mt8183: Add SCP work support ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34382/2/src/soc/mediatek/mt8183/scp... File src/soc/mediatek/mt8183/scp.c:
https://review.coreboot.org/c/coreboot/+/34382/2/src/soc/mediatek/mt8183/scp... PS2, Line 66: while (read32(&mt8183_scp->gpr0) != 0xaaaa) { braces {} are not necessary for single statement blocks
Attention is currently required from: Erin Lo. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34382 )
Change subject: WIP: mediatek/mt8183: Add SCP work support ......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2: please abandon this.
Attention is currently required from: Erin Lo. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34382 )
Change subject: WIP: mediatek/mt8183: Add SCP work support ......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2: please abandon this.
Julius Werner has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/34382 )
Change subject: WIP: mediatek/mt8183: Add SCP work support ......................................................................
Abandoned
obsolete
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