Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60016 )
Change subject: drivers/generic/bayhub_lv2: Add workaround for known errata ......................................................................
drivers/generic/bayhub_lv2: Add workaround for known errata
The Bayhub LV2 has a known errata wherein PCI config registers at offsets 0x234, 0x238, and 0x24C will only correctly accept writes when they are addressed via a DWORD (32-bit) wide write operation on the PCIe bus. Offset 0x234 is the LTR max snoop and max no-snoop latency register, therefore add a finalize callback to this driver which will program the LTR max-snoop/no-snoop register with a 32-bit write using the values from pciexp_get_ltr_max_latencies().
BUG=b:204343849 TEST=verified the PCI config space writes took effect on google/taeko
Change-Id: I1813f798faa534fb212cb1a074bc7bcadd17a517 Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/drivers/generic/bayhub_lv2/lv2.c 1 file changed, 21 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/60016/1
diff --git a/src/drivers/generic/bayhub_lv2/lv2.c b/src/drivers/generic/bayhub_lv2/lv2.c index 90e1e5d..2b48402 100644 --- a/src/drivers/generic/bayhub_lv2/lv2.c +++ b/src/drivers/generic/bayhub_lv2/lv2.c @@ -6,11 +6,30 @@ #include <device/device.h> #include <device/path.h> #include <device/pci.h> +#include <device/pciexp.h> #include <device/pci_ops.h> #include <device/pci_ids.h> #include "chip.h" #include "lv2.h"
+/* This chip has an errata where PCIe config space registers + 0x234, 0x248, and 0x24C only support DWORD access, therefore + reprogram these in the `finalize` callback. */ +static void lv2_enable_ltr(struct device *dev) +{ + u16 max_snoop, max_nosnoop; + if (!pciexp_get_ltr_max_latencies(dev, &max_snoop, &max_nosnoop)) + return; + + const unsigned int ltr_cap = pciexp_find_extended_cap(dev, PCIE_EXT_CAP_LTR_ID); + if (!ltr_cap) + return; + + pci_write_config32(dev, ltr_cap + PCI_LTR_MAX_SNOOP, (max_snoop << 16) | max_nosnoop); + printk(BIOS_INFO, "%s: Re-programmed LTR max latencies using chip-specific quirk\n", + dev_path(dev)); +} + static void lv2_enable(struct device *dev) { struct drivers_generic_bayhub_lv2_config *config = dev->chip_info; @@ -45,8 +64,10 @@ .enable_resources = pci_dev_enable_resources, .ops_pci = &pci_dev_ops_pci, .enable = lv2_enable, + .final = lv2_enable_ltr, };
+ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_O2_LV2, 0