[S] Change in coreboot[main]: mb/google/fatcat/var/fatcat: Implement barrel jack presence check

[Subrata Banik (Code Review)]

Attention is currently required from: Jayvik Desai, Kapil Porwal, Pranava Y N.

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87207?usp=email )

Change subject: mb/google/fatcat/var/fatcat: Implement barrel jack presence check
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mb/google/fatcat/var/fatcat: Implement barrel jack presence check

Uses fw_config to check if barrel jack PSU is configured. If
`PSU_BJ` is selected, checks hardware presence via
`google_chromeec_is_barrel_charger_present()`.

Allows 'fatcat' to adapt based on configured power source.

Includes:
- Adds `variant.c` to ramstage build in `Makefile.mk`.
- Adds `PSU` field (`PSU_USBC`: 0, `PSU_BJ`: 1) to `overridetree.cb`.
- Includes `ec.h` in `variant.c`.

TEST=Boot time savings ~62ms on google/fatcat with PSU=0 (USB-C).

Change-Id: I68507034cfbf4caa8e5c2ac9c7bebf758a5a5439
Signed-off-by: Subrata Banik 
---
M src/mainboard/google/fatcat/variants/fatcat/Makefile.mk
M src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
M src/mainboard/google/fatcat/variants/fatcat/variant.c
3 files changed, 14 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/87207/1

diff --git a/src/mainboard/google/fatcat/variants/fatcat/Makefile.mk b/src/mainboard/google/fatcat/variants/fatcat/Makefile.mk
index b9f1fd1..3fdd464 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/Makefile.mk
+++ b/src/mainboard/google/fatcat/variants/fatcat/Makefile.mk
@@ -6,4 +6,5 @@
 romstage-$(CONFIG_FW_CONFIG) += fw_config.c
 ramstage-y += gpio.c
 romstage-$(CONFIG_FW_CONFIG) += variant.c
+ramstage-$(CONFIG_FW_CONFIG) += variant.c
 ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
diff --git a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
index c6a63c3..e154ffc 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
@@ -67,6 +67,10 @@
    	option ISH_DISABLE		0
    	option ISH_ENABLE		1
    end
+	field PSU 25
+		option PSU_USBC			0
+		option PSU_BJ			1
+	end
 end

chip soc/intel/pantherlake
diff --git a/src/mainboard/google/fatcat/variants/fatcat/variant.c b/src/mainboard/google/fatcat/variants/fatcat/variant.c
index 5ba7683..3e0ee54 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/variant.c
+++ b/src/mainboard/google/fatcat/variants/fatcat/variant.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

#include <baseboard/variants.h>
+#include <ec/google/chromeec/ec.h>
 #include <fsp/api.h>
 #include <fw_config.h>
 #include <sar.h>
@@ -84,3 +85,11 @@
    	m_cfg->PchHdaSdiEnable[1] = false;
    }
 }
+
+bool variant_is_barrel_charger_present(void)
+{
+	if (fw_config_probe(FW_CONFIG(PSU, PSU_BJ)))
+		return google_chromeec_is_barrel_charger_present();
+	else
+		return false;
+}