[S] Change in coreboot[master]: soc/amd/common/block/lpc/lpc: don't report PCI config IO ports in LPC

[Felix Held (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger.

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74840 )

Change subject: soc/amd/common/block/lpc/lpc: don't report PCI config IO ports in LPC
......................................................................

soc/amd/common/block/lpc/lpc: don't report PCI config IO ports in LPC

The 2*4 IO ports from 0xcf8 to 0xcff are used for the IO-based PCI
config space access, so they wont be decoded to the LPC device and the
devices below it, so split the subtractive IO range of the LPC device
that those IO ports aren't covered by the subtractive IO regions of the
LPC device.

TEST=The coreboot console output on mandolin now shows the two
subtractive IO regions on the LPC device instead of the one that also
covered the PCI config IO ports:

PCI: 00:14.3 resource base 0 size 0 align 0 gran 0 limit cf7 flags 40040100 index 10000000
PCI: 00:14.3 resource base d00 size 0 align 0 gran 0 limit fff flags 40040100 index 10000100

The contents of /proc/mem are still identical.

Signed-off-by: Felix Held 
Change-Id: I67458dd14fa89d223e97c2410484c08654a6fab8
---
M src/soc/amd/common/block/lpc/lpc.c
1 file changed, 37 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/74840/1

diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c
index b8fb923..4a1151a 100644
--- a/src/soc/amd/common/block/lpc/lpc.c
+++ b/src/soc/amd/common/block/lpc/lpc.c
@@ -109,12 +109,21 @@
    /* Get the normal pci resources of this device */
    pci_dev_read_resources(dev);

-	/* Add an extra subtractive resource for both memory and I/O. */
+	/* Add subtractive resource for IO ports 0x0000 to 0x0cf7 */
    res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
    res->base = 0;
-	res->size = 0x1000;
+	res->limit = PCI_IO_CONFIG_INDEX - 1;
    res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
-		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+		     IORESOURCE_ASSIGNED;
+
+	/* IO ports 0x0cf8 to 0x0cff are used for PCI config space access */
+
+	/* Add subtractive resource for IO ports 0x0d00 to 0x0fff */
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
+	res->base = PCI_IO_CONFIG_INDEX + 2 * 4;
+	res->limit = 0x1000 - 1;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED;

/* Only up to 16 MByte of the SPI flash can be mapped right below 4 GB */
    mmio_range(dev, 1, FLASH_BELOW_4GB_MAPPING_REGION_BASE,