Change in coreboot[master]: soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard design

[Furquan Shaikh (Code Review)]

Attention is currently required from: Shreesh Chhabbi, Ravishankar Sarawadi, Duncan Laurie, Alex Levin, Sukumar Ghorai, Raj Astekar, Patrick Rudolph.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49766 )

Change subject: soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard design
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Patch Set 38: Code-Review+2

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/49766/comment/381233ab_72ed1f03 
PS38, Line 21: Deepest state expected on tigerlake up3 based
             : platforms is S0i3.1.
This is not correct. It is S0i3.2

https://review.coreboot.org/c/coreboot/+/49766/comment/358899f0_22cecbe8 
PS38, Line 26: S0i3.1
Volteer can reach S0i3.1 only because it uses CNVi.