Change in coreboot[master]: soc/intel/alderlake: Add HID for DPTF Power Participant

[Paul Fagerburg (Code Review)]

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63202 )

Change subject: soc/intel/alderlake: Add HID for DPTF Power Participant
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soc/intel/alderlake: Add HID for DPTF Power Participant

BUG=b:205928013
TEST=Build, boot brya0 and dump SSDT to check TPWR device HID

Signed-off-by: Varshit B Pandya 
Change-Id: I82507a3c0a521adbb8dec5520fd6d2ea3782c60e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63202
Tested-by: build bot (Jenkins) 
Reviewed-by: Eric Lai 
---
M src/soc/intel/alderlake/dptf.c
1 file changed, 2 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Eric Lai: Looks good to me, approved

diff --git a/src/soc/intel/alderlake/dptf.c b/src/soc/intel/alderlake/dptf.c
index 37754db..59243ba 100644
--- a/src/soc/intel/alderlake/dptf.c
+++ b/src/soc/intel/alderlake/dptf.c
@@ -12,6 +12,8 @@
    .fan_hid = "INTC1048",
    /* _HID for the toplevel TPCH device, typically _SB.TPCH */
    .tpch_device_hid = "INTC1049",
+	/* _HID for the toplevel TPWR device, typically _SB.DPTF.TPWR */
+	.tpwr_device_hid = "INTC1060",

.tpch_method_names = {
    	.set_fivr_low_clock_method = "RFC0",