Change in coreboot[master]: soc/intel/alderlake: support for PCIe slot & device detect timeout

[Jeremy Compostella (Code Review)]

Attention is currently required from: Bora Guvendik, Anil Kumar K, Cliff Huang, Subrata Banik, Tim Wawrzynczak.
Jeremy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63942 )

Change subject: soc/intel/alderlake: support for PCIe slot & device detect timeout
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Patch Set 6:

(2 comments)

File src/soc/intel/alderlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/63942/comment/6963ddef_1ffb2dbc 
PS6, Line 671: 		if (!!(rp_cfg->flags & PCIE_RP_BUILT_IN))
double negation is unnecessary in a if statement.
However, you could also write it:
s_cfg->PcieRpSlotImplemented[i] = !(rp_cfg->flags & PCIE_RP_BUILT_IN)

File src/soc/intel/common/block/include/intelblocks/pcie_rp.h:

https://review.coreboot.org/c/coreboot/+/63942/comment/fec24130_2b575261 
PS6, Line 30: 	/* indicates that this root port is built-in */
missing ending dot character.