Change in coreboot[master]: intel/tigerlake: Add Acoustic features - coreboot-gerrit

2 Mar 2021


      Attention is currently required from: Shaunak Saha, Caveh Jalali, Duncan Laurie, Nick Vaccaro, Patrick Rudolph.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50870 )
Change subject: intel/tigerlake: Add Acoustic features
......................................................................
Patch Set 3: Code-Review+2
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/50870/comment/bd7c4345_5541cc20 
PS3, Line 24: 
Can you also please mention here that TGL has a single VR domain(Vccin)? Hence, the chip config is updated to allow mainboards to set a single value instead of an array and FSP UPDs are accordingly set.
Patchset:
PS3: 
Thanks Shaunak!
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ica7f1f29995df33bdebb1fd55169cdb36f329ff8
Gerrit-Change-Number: 50870
Gerrit-PatchSet: 3
Gerrit-Owner: Shaunak Saha shaunak.saha@intel.com
Gerrit-Reviewer: Caveh Jalali caveh@chromium.org
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