Change in coreboot[master]: soc/intel/common/cpu: Update COS mask calculation for nem enhanced mode

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43494 )

Change subject: soc/intel/common/cpu: Update COS mask calculation for nem enhanced mode
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Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/43494/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/43494/3//COMMIT_MSG@20 
PS3, Line 20: 
            : Also the COS mask selection is mapped to bit 32:33 of MSR
            : IA32_PQR_ASSOC(0xC8F) and need to be updated in edx(maps 63:32) before
            : MSR write instead of eax(mas 31:0). This implementation corrects that
            : as well.
> I am checking on this, on the SKL, CNL, ICL it still maps to LSB. […]

Gotcha, thanks Aamir, I am finding the documentation around this register kind of confusing 😕