Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48767 )
Change subject: sb/intel/bd82x6x: Fix GNVS OperationRegion ......................................................................
sb/intel/bd82x6x: Fix GNVS OperationRegion
Structure with chromeos_acpi_t is expected to have size 0x1000.
Change-Id: I2eaa3a008566853b4144fa34ccffaa232d5d8e24 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/southbridge/intel/bd82x6x/acpi/globalnvs.asl 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/48767/1
diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl index 46096cc..ec193c4 100644 --- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl +++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl @@ -11,7 +11,7 @@ */
External(NVSA) -OperationRegion (GNVS, SystemMemory, NVSA, 0xf00) +OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48767 )
Change subject: sb/intel/bd82x6x: Fix GNVS OperationRegion ......................................................................
Patch Set 1: Code-Review+2
Hello build bot (Jenkins), Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48767
to look at the new patch set (#2).
Change subject: sb,soc/intel: Fix GNVS OperationRegion ......................................................................
sb,soc/intel: Fix GNVS OperationRegion
Structure with chromeos_acpi_t is expected to have size 0x1000. Only ones with device_nvs_t have size 0x2000.
Change-Id: I2eaa3a008566853b4144fa34ccffaa232d5d8e24 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/soc/intel/common/block/acpi/acpi/globalnvs.asl M src/soc/intel/denverton_ns/acpi/globalnvs.asl M src/soc/intel/skylake/acpi/globalnvs.asl M src/southbridge/intel/bd82x6x/acpi/globalnvs.asl M src/southbridge/intel/lynxpoint/acpi/globalnvs.asl 5 files changed, 5 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/48767/2
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48767 )
Change subject: sb,soc/intel: Fix GNVS OperationRegion ......................................................................
Patch Set 2: Code-Review+2
Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48767 )
Change subject: sb,soc/intel: Fix GNVS OperationRegion ......................................................................
sb,soc/intel: Fix GNVS OperationRegion
Structure with chromeos_acpi_t is expected to have size 0x1000. Only ones with device_nvs_t have size 0x2000.
Change-Id: I2eaa3a008566853b4144fa34ccffaa232d5d8e24 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/48767 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/common/block/acpi/acpi/globalnvs.asl M src/soc/intel/denverton_ns/acpi/globalnvs.asl M src/soc/intel/skylake/acpi/globalnvs.asl M src/southbridge/intel/bd82x6x/acpi/globalnvs.asl M src/southbridge/intel/lynxpoint/acpi/globalnvs.asl 5 files changed, 5 insertions(+), 5 deletions(-)
Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved
diff --git a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl index 826e718..1333857 100644 --- a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl +++ b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl @@ -13,7 +13,7 @@
External (NVSA)
-OperationRegion (GNVS, SystemMemory, NVSA, 0x2000) +OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ diff --git a/src/soc/intel/denverton_ns/acpi/globalnvs.asl b/src/soc/intel/denverton_ns/acpi/globalnvs.asl index 4725cec..bf880ed 100644 --- a/src/soc/intel/denverton_ns/acpi/globalnvs.asl +++ b/src/soc/intel/denverton_ns/acpi/globalnvs.asl @@ -12,7 +12,7 @@
External(NVSA) -OperationRegion (GNVS, SystemMemory, NVSA, 0x2000) +OperationRegion (GNVS, SystemMemory, NVSA, 0x100) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl index bc99698..913d2cf 100644 --- a/src/soc/intel/skylake/acpi/globalnvs.asl +++ b/src/soc/intel/skylake/acpi/globalnvs.asl @@ -13,7 +13,7 @@
External (NVSA)
-OperationRegion (GNVS, SystemMemory, NVSA, 0x2000) +OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl index 46096cc..ec193c4 100644 --- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl +++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl @@ -11,7 +11,7 @@ */
External(NVSA) -OperationRegion (GNVS, SystemMemory, NVSA, 0xf00) +OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ diff --git a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl index 482718a..d95d38a 100644 --- a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl +++ b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl @@ -12,7 +12,7 @@ */
External (NVSA) -OperationRegion (GNVS, SystemMemory, NVSA, 0xf00) +OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */
-
Angel Pons (Code Review) -
Hung-Te Lin (Code Review)
-
Kyösti Mälkki (Code Review)
-
Subrata Banik (Code Review)