Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48768 )
Change subject: ACPI: Fix some GNVS field comments ......................................................................
ACPI: Fix some GNVS field comments
Change-Id: I0d1e7b86d5b98da85bf539a4a3ec23e0eeaa4dfc Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/soc/intel/braswell/include/soc/nvs.h M src/soc/intel/broadwell/include/soc/nvs.h M src/soc/intel/common/block/include/intelblocks/nvs.h M src/soc/intel/skylake/include/soc/nvs.h 4 files changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/48768/1
diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h index 35ab47a..bc9b350 100644 --- a/src/soc/intel/braswell/include/soc/nvs.h +++ b/src/soc/intel/braswell/include/soc/nvs.h @@ -43,7 +43,7 @@ u8 rsvd2[8];
/* Base Addresses */ - u32 cmem; /* 0x30 - CBMEM TOC */ + u32 obsolete_cmem; /* 0x30 - CBMEM TOC */ u32 tolm; /* 0x34 - Top of Low Memory */ u32 cbmc; /* 0x38 - coreboot memconsole */ u8 rsvd3[120]; /* 0x3c - 0xb3 - unused */ diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h index afeed6f..4e2f3ea 100644 --- a/src/soc/intel/broadwell/include/soc/nvs.h +++ b/src/soc/intel/broadwell/include/soc/nvs.h @@ -32,7 +32,7 @@ u8 s33g; /* 0x15 - Enable 3G in S3 */ u8 lids; /* 0x16 - LID State */ u8 pwrs; /* 0x17 - AC Power State */ - u32 cmem; /* 0x18 - 0x1b - CBMEM TOC */ + u32 obsolete_cmem; /* 0x18 - 0x1b - CBMEM TOC */ u32 cbmc; /* 0x1c - 0x1f - coreboot Memory Console */ u64 pm1i; /* 0x20 - 0x27 - PM1 wake status bit */ u64 gpei; /* 0x28 - 0x2f - GPE wake status bit */ diff --git a/src/soc/intel/common/block/include/intelblocks/nvs.h b/src/soc/intel/common/block/include/intelblocks/nvs.h index cc240c5..bb02cf5 100644 --- a/src/soc/intel/common/block/include/intelblocks/nvs.h +++ b/src/soc/intel/common/block/include/intelblocks/nvs.h @@ -15,7 +15,7 @@ u8 tlvl; /* 0x05 - Throttle Level Limit */ u8 lids; /* 0x06 - LID State */ u8 pwrs; /* 0x07 - AC Power State */ - u32 cbmc; /* 0x08 - 0xb AC Power State */ + u32 cbmc; /* 0x08 - 0xb coreboot Memory Console */ u64 pm1i; /* 0x0c - 0x13 PM1 wake status bit */ u64 gpei; /* 0x14 - 0x1b GPE wake status bit */ u8 dpte; /* 0x1c - Enable DPTF */ diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h index 87f16fb..e1b99f2 100644 --- a/src/soc/intel/skylake/include/soc/nvs.h +++ b/src/soc/intel/skylake/include/soc/nvs.h @@ -31,7 +31,7 @@ u8 s33g; /* 0x15 - Enable 3G in S3 */ u8 lids; /* 0x16 - LID State */ u8 pwrs; /* 0x17 - AC Power State */ - u32 cmem; /* 0x18 - 0x1b - CBMEM TOC */ + u32 obsolete_cmem; /* 0x18 - 0x1b - CBMEM TOC */ u32 cbmc; /* 0x1c - 0x1f - coreboot Memory Console */ u64 pm1i; /* 0x20 - 0x27 - PM1 wake status bit */ u64 gpei; /* 0x28 - 0x2f - GPE wake status bit */
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48768 )
Change subject: ACPI: Fix some GNVS field comments ......................................................................
Patch Set 1: Code-Review+2
Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48768 )
Change subject: ACPI: Fix some GNVS field comments ......................................................................
ACPI: Fix some GNVS field comments
Change-Id: I0d1e7b86d5b98da85bf539a4a3ec23e0eeaa4dfc Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/48768 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/braswell/include/soc/nvs.h M src/soc/intel/broadwell/include/soc/nvs.h M src/soc/intel/common/block/include/intelblocks/nvs.h M src/soc/intel/skylake/include/soc/nvs.h 4 files changed, 4 insertions(+), 4 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h index 35ab47a..bc9b350 100644 --- a/src/soc/intel/braswell/include/soc/nvs.h +++ b/src/soc/intel/braswell/include/soc/nvs.h @@ -43,7 +43,7 @@ u8 rsvd2[8];
/* Base Addresses */ - u32 cmem; /* 0x30 - CBMEM TOC */ + u32 obsolete_cmem; /* 0x30 - CBMEM TOC */ u32 tolm; /* 0x34 - Top of Low Memory */ u32 cbmc; /* 0x38 - coreboot memconsole */ u8 rsvd3[120]; /* 0x3c - 0xb3 - unused */ diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h index afeed6f..4e2f3ea 100644 --- a/src/soc/intel/broadwell/include/soc/nvs.h +++ b/src/soc/intel/broadwell/include/soc/nvs.h @@ -32,7 +32,7 @@ u8 s33g; /* 0x15 - Enable 3G in S3 */ u8 lids; /* 0x16 - LID State */ u8 pwrs; /* 0x17 - AC Power State */ - u32 cmem; /* 0x18 - 0x1b - CBMEM TOC */ + u32 obsolete_cmem; /* 0x18 - 0x1b - CBMEM TOC */ u32 cbmc; /* 0x1c - 0x1f - coreboot Memory Console */ u64 pm1i; /* 0x20 - 0x27 - PM1 wake status bit */ u64 gpei; /* 0x28 - 0x2f - GPE wake status bit */ diff --git a/src/soc/intel/common/block/include/intelblocks/nvs.h b/src/soc/intel/common/block/include/intelblocks/nvs.h index cc240c5..bb02cf5 100644 --- a/src/soc/intel/common/block/include/intelblocks/nvs.h +++ b/src/soc/intel/common/block/include/intelblocks/nvs.h @@ -15,7 +15,7 @@ u8 tlvl; /* 0x05 - Throttle Level Limit */ u8 lids; /* 0x06 - LID State */ u8 pwrs; /* 0x07 - AC Power State */ - u32 cbmc; /* 0x08 - 0xb AC Power State */ + u32 cbmc; /* 0x08 - 0xb coreboot Memory Console */ u64 pm1i; /* 0x0c - 0x13 PM1 wake status bit */ u64 gpei; /* 0x14 - 0x1b GPE wake status bit */ u8 dpte; /* 0x1c - Enable DPTF */ diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h index 87f16fb..e1b99f2 100644 --- a/src/soc/intel/skylake/include/soc/nvs.h +++ b/src/soc/intel/skylake/include/soc/nvs.h @@ -31,7 +31,7 @@ u8 s33g; /* 0x15 - Enable 3G in S3 */ u8 lids; /* 0x16 - LID State */ u8 pwrs; /* 0x17 - AC Power State */ - u32 cmem; /* 0x18 - 0x1b - CBMEM TOC */ + u32 obsolete_cmem; /* 0x18 - 0x1b - CBMEM TOC */ u32 cbmc; /* 0x1c - 0x1f - coreboot Memory Console */ u64 pm1i; /* 0x20 - 0x27 - PM1 wake status bit */ u64 gpei; /* 0x28 - 0x2f - GPE wake status bit */
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Angel Pons (Code Review) -
Hung-Te Lin (Code Review)
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Kyösti Mälkki (Code Review)