Change in coreboot[master]: mb/g/drallion: Clean up none used weak function

[EricR Lai (Code Review)]

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37780 )

Change subject: mb/g/drallion: Clean up none used weak function
......................................................................

mb/g/drallion: Clean up none used weak function

Drallion only support on board dimm. Remove the spd read from
smbus. Since remove the Wlico 1.0 CML variants, weak function
is not needed.

BUG=b:140068267
TEST=boot into OS without issue
BRANCH=none

Signed-off-by: Eric Lai 
Change-Id: I662f87ccf48ba470998fa28fb14c9985673cb37d
---
M src/mainboard/google/drallion/romstage.c
1 file changed, 0 insertions(+), 45 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/37780/1

diff --git a/src/mainboard/google/drallion/romstage.c b/src/mainboard/google/drallion/romstage.c
index 03bc17f..ed9923f 100644
--- a/src/mainboard/google/drallion/romstage.c
+++ b/src/mainboard/google/drallion/romstage.c
@@ -18,51 +18,6 @@
 #include <soc/romstage.h>
 #include <baseboard/variants.h>

-void __weak variant_mainboard_post_init_params(FSPM_UPD *mupd) {}
-
-static const struct cnl_mb_cfg memcfg = {
-	/* Access memory info through SMBUS. */
-	.spd[0] = {
-		.read_type = READ_SMBUS,
-		.spd_spec = {.spd_smbus_address = 0xa0},
-	},
-	.spd[1] = {.read_type = NOT_EXISTING},
-	.spd[2] = {
-		.read_type = READ_SMBUS,
-		.spd_spec = {.spd_smbus_address = 0xa4},
-	},
-	.spd[3] = {.read_type = NOT_EXISTING},
-
-	/*
-	 * The dqs_map arrays map the ddr4 pins to the SoC pins
-	 * for both channels.
-	 *
-	 * the index = pin number on ddr4 part
-	 * the value = pin number on SoC
-	 */
-	.dqs_map[DDR_CH0] = {0, 1, 4, 5, 2, 3, 6, 7},
-	.dqs_map[DDR_CH1] = {0, 1, 4, 5, 2, 3, 6, 7},
-
-	/* Baseboard uses 121, 81 and 100 rcomp resistors */
-	.rcomp_resistor = {121, 81, 100},
-
-	/*
-	 * Baseboard Rcomp target values.
-	 */
-	.rcomp_targets = {100, 40, 20, 20, 26},
-
-	/* Disable Early Command Training */
-	.ect = 0,
-
-	/* Base on board design */
-	.vref_ca_config = 2,
-};
-
-const struct cnl_mb_cfg * __weak get_variant_memory_cfg(struct cnl_mb_cfg *mem_cfg)
-{
-	return &memcfg;
-}
-
 void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
    struct cnl_mb_cfg board_memcfg;

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37780 )

Change subject: mb/g/drallion: Clean up none used weak function
......................................................................

Patch Set 1:

(5 comments)

https://review.coreboot.org/c/coreboot/+/37780/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/37780/1//COMMIT_MSG@7 
PS1, Line 7: none used
unused

https://review.coreboot.org/c/coreboot/+/37780/1//COMMIT_MSG@9 
PS1, Line 9: support
supports

https://review.coreboot.org/c/coreboot/+/37780/1//COMMIT_MSG@10 
PS1, Line 10: Since remove the Wlico 1.0 CML variants
What do you mean?
> Since the removal of the Wilco 1.0 CML variants, …

Please add the commit, where this was removed.

https://review.coreboot.org/c/coreboot/+/37780/1//COMMIT_MSG@10 
PS1, Line 10: Wlico
Wilco

https://review.coreboot.org/c/coreboot/+/37780/1//COMMIT_MSG@10 
PS1, Line 10: smbus
SMBus

Change in coreboot[master]: mb/g/drallion: Clean up none unused weak function

[EricR Lai (Code Review)]

Hello Mathew King, Duncan Laurie, Mike Wiitala, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/37780

to look at the new patch set (#2).

Change subject: mb/g/drallion: Clean up none unused weak function
......................................................................

mb/g/drallion: Clean up none unused weak function

Drallion only supports on board dimm. Remove the spd read from
SMbus. Since CB:37678 remove the Wilco 1.0 CML variants, weak function
is not needed.

BUG=b:140068267
TEST=boot into OS without issue
BRANCH=none

Signed-off-by: Eric Lai 
Change-Id: I662f87ccf48ba470998fa28fb14c9985673cb37d
---
M src/mainboard/google/drallion/romstage.c
1 file changed, 0 insertions(+), 45 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/37780/2

Change in coreboot[master]: mb/g/drallion: Clean up none unused weak function

[EricR Lai (Code Review)]

EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37780 )

Change subject: mb/g/drallion: Clean up none unused weak function
......................................................................

Patch Set 2:

(5 comments)

https://review.coreboot.org/c/coreboot/+/37780/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/37780/1//COMMIT_MSG@7 
PS1, Line 7: none used
> unused

Done

https://review.coreboot.org/c/coreboot/+/37780/1//COMMIT_MSG@9 
PS1, Line 9: support
> supports

Done

https://review.coreboot.org/c/coreboot/+/37780/1//COMMIT_MSG@10 
PS1, Line 10: smbus
> SMBus

Done

https://review.coreboot.org/c/coreboot/+/37780/1//COMMIT_MSG@10 
PS1, Line 10: Wlico
> Wilco

Done

https://review.coreboot.org/c/coreboot/+/37780/1//COMMIT_MSG@10 
PS1, Line 10: Since remove the Wlico 1.0 CML variants
> What do you mean? […]

Done

Change in coreboot[master]: mb/google/drallion: Clean up none unused weak function

[EricR Lai (Code Review)]

Hello Mathew King, Duncan Laurie, Mike Wiitala, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/37780

to look at the new patch set (#3).

Change subject: mb/google/drallion: Clean up none unused weak function
......................................................................

mb/google/drallion: Clean up none unused weak function

Drallion only supports on board dimm. Remove the spd read from
SMbus. Since CB:37678 remove the Wilco 1.0 CML variants, weak function
is not needed.

BUG=b:140068267
TEST=boot into OS without issue
BRANCH=none

Signed-off-by: Eric Lai 
Change-Id: I662f87ccf48ba470998fa28fb14c9985673cb37d
---
M src/mainboard/google/drallion/romstage.c
1 file changed, 0 insertions(+), 45 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/37780/3

Change in coreboot[master]: mb/google/drallion: Clean up none unused weak function

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37780 )

Change subject: mb/google/drallion: Clean up none unused weak function
......................................................................

Patch Set 3:

(2 comments)

https://review.coreboot.org/c/coreboot/+/37780/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/37780/3//COMMIT_MSG@7 
PS3, Line 7: none unused
The *none* needs to be removed too.
> Clean up unused weak function

https://review.coreboot.org/c/coreboot/+/37780/3//COMMIT_MSG@10 
PS3, Line 10: SMbus
SMBus

http://smbus.org/

Change in coreboot[master]: mb/google/drallion: Clean up unused weak function

[EricR Lai (Code Review)]

Hello Mathew King, Duncan Laurie, Mike Wiitala, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/37780

to look at the new patch set (#4).

Change subject: mb/google/drallion: Clean up unused weak function
......................................................................

mb/google/drallion: Clean up unused weak function

Drallion only supports on board dimm. Remove the spd read from
SMBus. Since CB:37678 remove the Wilco 1.0 CML variants, weak function
is not needed.

BUG=b:140068267
TEST=boot into OS without issue
BRANCH=none

Signed-off-by: Eric Lai 
Change-Id: I662f87ccf48ba470998fa28fb14c9985673cb37d
---
M src/mainboard/google/drallion/romstage.c
1 file changed, 0 insertions(+), 45 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/37780/4

Change in coreboot[master]: mb/google/drallion: Clean up unused weak function

[EricR Lai (Code Review)]

EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37780 )

Change subject: mb/google/drallion: Clean up unused weak function
......................................................................

Patch Set 4:

(2 comments)

https://review.coreboot.org/c/coreboot/+/37780/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/37780/3//COMMIT_MSG@7 
PS3, Line 7: none unused
> The *none* needs to be removed too. […]

thx

https://review.coreboot.org/c/coreboot/+/37780/3//COMMIT_MSG@10 
PS3, Line 10: SMbus
> SMBus […]

Done

Change in coreboot[master]: mb/google/drallion: Clean up unused weak function

[Mathew King (Code Review)]

Mathew King has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37780 )

Change subject: mb/google/drallion: Clean up unused weak function
......................................................................

Patch Set 4: Code-Review+2

Change in coreboot[master]: mb/google/drallion: Clean up unused weak function

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37780 )

Change subject: mb/google/drallion: Clean up unused weak function
......................................................................

mb/google/drallion: Clean up unused weak function

Drallion only supports on board dimm. Remove the spd read from
SMBus. Since CB:37678 remove the Wilco 1.0 CML variants, weak function
is not needed.

BUG=b:140068267
TEST=boot into OS without issue
BRANCH=none

Signed-off-by: Eric Lai 
Change-Id: I662f87ccf48ba470998fa28fb14c9985673cb37d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37780
Reviewed-by: Mathew King 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/google/drallion/romstage.c
1 file changed, 0 insertions(+), 45 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Mathew King: Looks good to me, approved

diff --git a/src/mainboard/google/drallion/romstage.c b/src/mainboard/google/drallion/romstage.c
index 03bc17f..ed9923f 100644
--- a/src/mainboard/google/drallion/romstage.c
+++ b/src/mainboard/google/drallion/romstage.c
@@ -18,51 +18,6 @@
 #include <soc/romstage.h>
 #include <baseboard/variants.h>

-void __weak variant_mainboard_post_init_params(FSPM_UPD *mupd) {}
-
-static const struct cnl_mb_cfg memcfg = {
-	/* Access memory info through SMBUS. */
-	.spd[0] = {
-		.read_type = READ_SMBUS,
-		.spd_spec = {.spd_smbus_address = 0xa0},
-	},
-	.spd[1] = {.read_type = NOT_EXISTING},
-	.spd[2] = {
-		.read_type = READ_SMBUS,
-		.spd_spec = {.spd_smbus_address = 0xa4},
-	},
-	.spd[3] = {.read_type = NOT_EXISTING},
-
-	/*
-	 * The dqs_map arrays map the ddr4 pins to the SoC pins
-	 * for both channels.
-	 *
-	 * the index = pin number on ddr4 part
-	 * the value = pin number on SoC
-	 */
-	.dqs_map[DDR_CH0] = {0, 1, 4, 5, 2, 3, 6, 7},
-	.dqs_map[DDR_CH1] = {0, 1, 4, 5, 2, 3, 6, 7},
-
-	/* Baseboard uses 121, 81 and 100 rcomp resistors */
-	.rcomp_resistor = {121, 81, 100},
-
-	/*
-	 * Baseboard Rcomp target values.
-	 */
-	.rcomp_targets = {100, 40, 20, 20, 26},
-
-	/* Disable Early Command Training */
-	.ect = 0,
-
-	/* Base on board design */
-	.vref_ca_config = 2,
-};
-
-const struct cnl_mb_cfg * __weak get_variant_memory_cfg(struct cnl_mb_cfg *mem_cfg)
-{
-	return &memcfg;
-}
-
 void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
    struct cnl_mb_cfg board_memcfg;