Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29903
Change subject: soc/intel/apl: Enable graphics with libgfxinit ......................................................................
soc/intel/apl: Enable graphics with libgfxinit
As usual, it just works.
Change-Id: I7b111f1cdac4d18f2fc3089f57aebf3ad1739e5d Signed-off-by: Nico Huber nico.huber@secunet.com --- M src/drivers/intel/gma/Kconfig M src/soc/intel/apollolake/graphics.c 2 files changed, 27 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/29903/1
diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index 10ccf71..a5c8495 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -68,13 +68,14 @@ depends on NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_X4X \ || NORTHBRIDGE_INTEL_NEHALEM || NORTHBRIDGE_INTEL_SANDYBRIDGE \ || NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_HASWELL \ - || SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE + || SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE || SOC_INTEL_APOLLOLAKE depends on MAINBOARD_HAS_LIBGFXINIT
if GFX_GMA
config GFX_GMA_CPU string + default "Broxton" if SOC_INTEL_APOLLOLAKE default "Skylake" if SOC_INTEL_SKYLAKE default "Broadwell" if SOC_INTEL_BROADWELL default "Haswell" if NORTHBRIDGE_INTEL_HASWELL diff --git a/src/soc/intel/apollolake/graphics.c b/src/soc/intel/apollolake/graphics.c index 4857788..37cdda4 100644 --- a/src/soc/intel/apollolake/graphics.c +++ b/src/soc/intel/apollolake/graphics.c @@ -15,19 +15,44 @@ * GNU General Public License for more details. */
+#include <stdint.h> +#include <arch/acpi.h> #include <arch/acpigen.h> +#include <bootmode.h> #include <console/console.h> #include <fsp/util.h> #include <device/device.h> #include <device/pci.h> #include <intelblocks/graphics.h> #include <drivers/intel/gma/opregion.h> +#include <drivers/intel/gma/libgfxinit.h>
uintptr_t fsp_soc_get_igd_bar(void) { return graphics_get_memory_base(); }
+void graphics_soc_init(struct device *const dev) +{ + if (IS_ENABLED(CONFIG_RUN_FSP_GOP)) + return; + + uint32_t reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_MASTER; + pci_write_config32(dev, PCI_COMMAND, reg32); + + if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) { + if (!acpi_is_wakeup_s3() && display_init_required()) { + int lightup_ok; + gma_gfxinit(&lightup_ok); + gfx_set_init_done(lightup_ok); + } + } else { + /* Initialize PCI device, load/execute BIOS Option ROM */ + pci_dev_init(dev); + } +} + uintptr_t graphics_soc_write_acpi_opregion(struct device *device, uintptr_t current, struct acpi_rsdp *rsdp) {