Attention is currently required from: Kane Chen. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63486 )
Change subject: soc/intel/common: Enable rom cache on all CPU threads ......................................................................
Patch Set 2:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63486/comment/01434674_c79ddee3 PS2, Line 11: wait all … wait for all …
https://review.coreboot.org/c/coreboot/+/63486/comment/14378c56_cf021016 PS2, Line 11: However the BSP doesn't wait all threads to finish _x86_setup_mtrrs Please add a blank line between paragraphs, or do *not* break lines, just because a new sentence starts.
https://review.coreboot.org/c/coreboot/+/63486/comment/e925d43b_a5d645d8 PS2, Line 12: run runs
https://review.coreboot.org/c/coreboot/+/63486/comment/1c7959ba_0f71ba52 PS2, Line 22: conditionm condition
https://review.coreboot.org/c/coreboot/+/63486/comment/a48437e9_6fc6f5c9 PS2, Line 30: TEST=Tested on gimble and found rom cache is set properly right before How can you check that exactly?
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Paul Menzel (Code Review)