Change in coreboot[master]: soc/amd/cezanne/fch: add PCIe GPP clock generator configuration settings - coreboot-gerrit

18 May 2021


      Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held.
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54632 )
Change subject: soc/amd/cezanne/fch: add PCIe GPP clock generator configuration settings
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Patch Set 1: Code-Review+2
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ib6a49a026a6cac29e3f1ad83c82bf9930c277a6a
Gerrit-Change-Number: 54632
Gerrit-PatchSet: 1
Gerrit-Owner: Felix Held felix-coreboot@felixheld.de
Gerrit-Reviewer: Jason Glenesk jason.glenesk@gmail.com
Gerrit-Reviewer: Marshall Dawson marshalldawson3rd@gmail.com
Gerrit-Reviewer: Raul Rangel rrangel@chromium.org
Gerrit-Attention: Jason Glenesk jason.glenesk@gmail.com
Gerrit-Attention: Marshall Dawson marshalldawson3rd@gmail.com
Gerrit-Attention: Felix Held felix-coreboot@felixheld.de
Gerrit-Comment-Date: Tue, 18 May 2021 16:04:05 +0000
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