Change in coreboot[master]: [TEST,NOTFORMERGE]cpu/intel/car: Test setting XIP CACHE during CAR
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35722 )
Change subject: [TEST,NOTFORMERGE]cpu/intel/car: Test setting XIP CACHE during CAR ......................................................................
[TEST,NOTFORMERGE]cpu/intel/car: Test setting XIP CACHE during CAR
Totest: Does it still boot? Are romstage timestamps affected (does caching work)?
Change-Id: I424e3804442b823880f89dcee9d1478cebb55bde Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/intel/car/romstage.c A src/cpu/intel/car/set_mtrr.S A src/cpu/intel/car/set_mtrr.h M src/cpu/intel/socket_LGA775/Makefile.inc 4 files changed, 102 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/35722/1
diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index 547b121..eee3412 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -15,12 +15,17 @@ #include <arch/romstage.h> #include <bootblock_common.h> #include <console/console.h> +#include <cpu/x86/msr.h> +#include <cpu/cpu.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <arch/symbols.h> #include <commonlib/helpers.h> #include <program_loading.h> #include <timestamp.h> +#include <symbols.h> +#include <lib.h> +#include "../car/set_mtrr.h"
/* If we do not have a constrained _car_stack region size, use the following as a guideline for acceptable stack usage. */ @@ -51,6 +56,15 @@ for (i = 0; i < num_guards; i++) stack_base[i] = stack_guard;
+ u32 program_size = _eprogram - _program; + program_size = 1 << log2_ceil(program_size); + msr_t mtrr_phys_mask; + mtrr_phys_mask.lo = ~(program_size - 1) | MTRR_PHYS_MASK_VALID; + mtrr_phys_mask.hi = (1 << (cpu_phys_address_size() - 32)) - 1; + + set_mtrr_asm(1, ALIGN_DOWN((u32)_program, program_size) | MTRR_TYPE_WRPROT, + mtrr_phys_mask); + mainboard_romstage_entry();
/* Check the stack. */ diff --git a/src/cpu/intel/car/set_mtrr.S b/src/cpu/intel/car/set_mtrr.S new file mode 100644 index 0000000..de8a242 --- /dev/null +++ b/src/cpu/intel/car/set_mtrr.S @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/post_code.h> + +.global set_mtrr_asm + /* ARG0: MTRR_NUM to use (1 dword) + * ARG1: BASE_ARG (1 dword) + * ARG2: MASK_ARG (2 dwords) + * All arguments assume sanity from the caller + */ +.code32 +set_mtrr_asm: + push %ebp + movl %esp, %ebp + push %edi + push %esi + push %ebx + movl (%ebp), %ecx // MTRR_NUM + movl 4(%ebp), %edi // BASE + movl 8(%ebp), %esi // MASK_LO + movl 12(%ebp), %ebx // MASK_HI + + /* Enable Cache-as-RAM mode by disabling cache. + Assume fetching from stack does not work */ + movl %cr0, %eax + orl $CR0_CacheDisable, %eax + movl %eax, %cr0 + + imul $2, %ecx, %ecx + addl $MTRR_PHYS_BASE(0), %ecx + + // MTRR_PHYS_BASE + xorl %edx, %edx + movl %edi, %eax + wrmsr + + // MTRR_PHYS_MASK + addl $1, %ecx + movl %esi, %eax + movl %ebx, %edx + wrmsr + + /* Enable cache again. */ + movl %cr0, %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax + movl %eax, %cr0 + + /* restore regs */ + pop %ebx + pop %esi + pop %edi + pop %ebp + ret diff --git a/src/cpu/intel/car/set_mtrr.h b/src/cpu/intel/car/set_mtrr.h new file mode 100644 index 0000000..41bc430 --- /dev/null +++ b/src/cpu/intel/car/set_mtrr.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SET_MTRR_H +#define _SET_MTRR_H + +#include <cpu/x86/msr.h> + +void set_mtrr_asm(int num_mtrr, u32 phys_base, msr_t phys_mask); + +#endif diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc index ceb084c..fd0d642 100644 --- a/src/cpu/intel/socket_LGA775/Makefile.inc +++ b/src/cpu/intel/socket_LGA775/Makefile.inc @@ -14,6 +14,7 @@ subdirs-y += ../speedstep
cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S +romstage-y += ../car/set_mtrr.S postcar-y += ../car/p4-netburst/exit_car.S
romstage-y += ../car/romstage.c
Hello Patrick Rudolph, Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35722
to look at the new patch set (#2).
Change subject: [TEST,NOTFORMERGE]cpu/intel/car: Test setting XIP CACHE during CAR ......................................................................
[TEST,NOTFORMERGE]cpu/intel/car: Test setting XIP CACHE during CAR
Totest: Does it still boot? Are romstage timestamps affected (does caching work)?
Change-Id: I424e3804442b823880f89dcee9d1478cebb55bde Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/intel/car/p4-netburst/cache_as_ram.S M src/cpu/intel/car/romstage.c A src/cpu/intel/car/set_mtrr.S A src/cpu/intel/car/set_mtrr.h M src/cpu/intel/socket_LGA775/Makefile.inc 5 files changed, 106 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/35722/2
Hello Patrick Rudolph, Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35722
to look at the new patch set (#3).
Change subject: [TEST,NOTFORMERGE]cpu/intel/car: Test setting XIP CACHE during CAR ......................................................................
[TEST,NOTFORMERGE]cpu/intel/car: Test setting XIP CACHE during CAR
Totest: Does it still boot? Are romstage timestamps affected (does caching work)?
It does work and the CR0 bits don't even seem necessary.
Change-Id: I424e3804442b823880f89dcee9d1478cebb55bde Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/intel/car/p4-netburst/cache_as_ram.S M src/cpu/intel/car/romstage.c A src/cpu/intel/car/set_mtrr.S A src/cpu/intel/car/set_mtrr.h M src/cpu/intel/socket_LGA775/Makefile.inc 5 files changed, 108 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/35722/3
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35722 )
Change subject: [TEST,NOTFORMERGE]cpu/intel/car: Test setting XIP CACHE during CAR ......................................................................
Patch Set 3: Code-Review-2
Arthur Heymans has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/35722 )
Change subject: [TEST,NOTFORMERGE]cpu/intel/car: Test setting XIP CACHE during CAR ......................................................................
Abandoned
-
Arthur Heymans (Code Review)