Arthur Heymans uploaded patch set #3 to this change.

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[TEST,NOTFORMERGE]cpu/intel/car: Test setting XIP CACHE during CAR

Totest: Does it still boot? Are romstage timestamps affected (does
caching work)?

It does work and the CR0 bits don't even seem necessary.

Change-Id: I424e3804442b823880f89dcee9d1478cebb55bde
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
---
M src/cpu/intel/car/p4-netburst/cache_as_ram.S
M src/cpu/intel/car/romstage.c
A src/cpu/intel/car/set_mtrr.S
A src/cpu/intel/car/set_mtrr.h
M src/cpu/intel/socket_LGA775/Makefile.inc
5 files changed, 108 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/35722/3

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