Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40524 )
Change subject: mb/ocp/tiogapass: Populate SMBIOS type 11 OEM data ......................................................................
mb/ocp/tiogapass: Populate SMBIOS type 11 OEM data
1. Populate SMBIOS type 11 OEM data according to OEM specification. 2. Set the read PPIN MSR for CPU0 and CPU1 to BMC.
Tested on OCP Tioga Pass. Signed-off-by: Johnny Lin johnny_lin@wiwynn.com
Change-Id: Ie11ab68267438ea9c669c809985c0c2d7578280e --- M src/mainboard/ocp/tiogapass/Makefile.inc A src/mainboard/ocp/tiogapass/ipmi.c A src/mainboard/ocp/tiogapass/ipmi.h M src/mainboard/ocp/tiogapass/ramstage.c 4 files changed, 111 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/40524/1
diff --git a/src/mainboard/ocp/tiogapass/Makefile.inc b/src/mainboard/ocp/tiogapass/Makefile.inc index 27370fd..33ae2ff 100644 --- a/src/mainboard/ocp/tiogapass/Makefile.inc +++ b/src/mainboard/ocp/tiogapass/Makefile.inc @@ -15,6 +15,7 @@
bootblock-y += bootblock.c ramstage-y += ramstage.c +ramstage-y += ipmi.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
CPPFLAGS_common += -Isrc/mainboard/$(MAINBOARDDIR)/ diff --git a/src/mainboard/ocp/tiogapass/ipmi.c b/src/mainboard/ocp/tiogapass/ipmi.c new file mode 100644 index 0000000..7d98c0c --- /dev/null +++ b/src/mainboard/ocp/tiogapass/ipmi.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <stdint.h> +#include <drivers/ipmi/ipmi_kcs.h> +#include <console/console.h> +#include "ipmi.h" + +void ipmi_set_ppin(struct ppin_req *req) +{ + int ret; + struct ipmi_rsp rsp; + + ret = ipmi_kcs_message(BMC_KCS_BASE, IPMI_NETFN_OEM, 0x0, IPMI_OEM_SET_PPIN, + (const unsigned char *) req, sizeof(*req), + (unsigned char *) &rsp, sizeof(rsp)); + + if (ret < sizeof(struct ipmi_rsp) || rsp.completion_code) { + printk(BIOS_ERR, "IPMI: %s command failed (ret=%d resp=0x%x)\n", + __func__, ret, rsp.completion_code); + return; + } + printk(BIOS_INFO, "IPMI Set PPIN done.\n"); +} diff --git a/src/mainboard/ocp/tiogapass/ipmi.h b/src/mainboard/ocp/tiogapass/ipmi.h new file mode 100644 index 0000000..f8a98c9 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/ipmi.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef TIOGAPASS_IPMI_H +#define TIOGAPASS_IPMI_H +#include <types.h> +#include <drivers/ipmi/ipmi_ops.h> + +#define IPMI_NETFN_OEM 0x30 +#define IPMI_OEM_SET_PPIN 0x77 + +#define BMC_KCS_BASE 0xca2 + +/* PPIN for 2 CPU IPMI request */ +struct ppin_req { + uint32_t CPU0lo; + uint32_t CPU0hi; + uint32_t CPU1lo; + uint32_t CPU1hi; +} __packed; +/* Send CPU0 and CPU1 PPIN to BMC */ +void ipmi_set_ppin(struct ppin_req *req); +#endif diff --git a/src/mainboard/ocp/tiogapass/ramstage.c b/src/mainboard/ocp/tiogapass/ramstage.c index 4820ed4..61d6aef 100644 --- a/src/mainboard/ocp/tiogapass/ramstage.c +++ b/src/mainboard/ocp/tiogapass/ramstage.c @@ -16,17 +16,17 @@ #include <bootstate.h> #include <gpio.h> #include <soc/lewisburg_pch_gpio_defs.h> +#include <soc/msr.h> #include <smbios.h> #include <drivers/ipmi/ipmi_ops.h> +#include "ipmi.h"
#define FRU_DEVICE_ID 0 -#define BMC_KCS_BASE 0xca2
static struct fru_info_str fru_strings;
void mainboard_silicon_init_params(FSPS_UPD *params) { - read_fru_areas(BMC_KCS_BASE, FRU_DEVICE_ID, 0, &fru_strings); }
/* Override SMBIOS type 1 data. */ @@ -148,4 +148,65 @@ gpio_output(GPP_B20, 0); }
+/* Override SMBIOS type 11 OEM string */ +static void mainboard_smbios_strings(struct device *dev, struct smbios_type11 *t) +{ + char ppin[17]; + char blank[] = " "; + + /* Add OEM string 1 to 3 */ + if (*fru_strings.board_info.board_custom != NULL) + t->count = smbios_add_string(t->eos, *fru_strings.board_info.board_custom); + else + t->count = smbios_add_string(t->eos, blank); + if (*fru_strings.prod_info.product_custom != NULL) + t->count = smbios_add_string(t->eos, *fru_strings.prod_info.product_custom); + else + t->count = smbios_add_string(t->eos, blank); + + if (*(fru_strings.prod_info.product_custom + 1) != NULL) + t->count = smbios_add_string(t->eos, + *(fru_strings.prod_info.product_custom + 1)); + else + t->count = smbios_add_string(t->eos, blank); + + /* Add blank for OEM String 4 */ + t->count = smbios_add_string(t->eos, blank); + /* Add CPU0 and CPU1 PPIN to OEM string 5 and 6. */ + snprintf(ppin, sizeof(ppin), "%x%x", xeon_sp_ppin[0].hi, xeon_sp_ppin[0].lo); + t->count = smbios_add_string(t->eos, ppin); + snprintf(ppin, sizeof(ppin), "%x%x", xeon_sp_ppin[1].hi, xeon_sp_ppin[1].lo); + t->count = smbios_add_string(t->eos, ppin); + /* Add OEM string 7 */ + if (*(fru_strings.board_info.board_custom + 1) != NULL) + t->count = smbios_add_string(t->eos, + *(fru_strings.board_info.board_custom + 1)); + else + t->count = smbios_add_string(t->eos, blank); +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->get_smbios_strings = mainboard_smbios_strings, + + read_fru_areas(BMC_KCS_BASE, FRU_DEVICE_ID, 0, &fru_strings); +} + +static void mainboard_final(void *chip_info) +{ + struct ppin_req req; + + req.CPU0lo = xeon_sp_ppin[0].lo; + req.CPU0hi = xeon_sp_ppin[0].hi; + req.CPU1lo = xeon_sp_ppin[1].lo; + req.CPU1hi = xeon_sp_ppin[1].hi; + /* Set PPIN to BMC */ + ipmi_set_ppin(&req); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, + .final = mainboard_final, +}; + BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, pull_post_complete_pin, NULL);
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40524 )
Change subject: mb/ocp/tiogapass: Populate SMBIOS type 11 OEM data ......................................................................
Patch Set 2:
(3 comments)
https://review.coreboot.org/c/coreboot/+/40524/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/40524/2//COMMIT_MSG@14 PS2, Line 14: Please remove the blank line.
https://review.coreboot.org/c/coreboot/+/40524/2/src/mainboard/ocp/tiogapass... File src/mainboard/ocp/tiogapass/ipmi.h:
https://review.coreboot.org/c/coreboot/+/40524/2/src/mainboard/ocp/tiogapass... PS2, Line 16: uint32_t CPU0lo; coreboot prefers lowercase variable names.
https://review.coreboot.org/c/coreboot/+/40524/2/src/mainboard/ocp/tiogapass... File src/mainboard/ocp/tiogapass/ipmi.c:
https://review.coreboot.org/c/coreboot/+/40524/2/src/mainboard/ocp/tiogapass... PS2, Line 23: printk(BIOS_INFO, "IPMI Set PPIN done.\n"); The current style suggests, it’s a debug message. For BIOS_INFO, please improve the wording.
Hello build bot (Jenkins), Andrey Petrov, Patrick Georgi, Martin Roth, Jonathan Zhang, David Hendricks, Jingle Hsu, Morgan Jang,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40524
to look at the new patch set (#3).
Change subject: mb/ocp/tiogapass: Populate SMBIOS data and set the read PPIN to BMC ......................................................................
mb/ocp/tiogapass: Populate SMBIOS data and set the read PPIN to BMC
1. Populate SMBIOS data from OCP_DMI driver read from FRU 2. Set the read PPIN MSR for CPU0 and CPU1 to BMC.
Tested on OCP Tioga Pass.
Signed-off-by: Johnny Lin johnny_lin@wiwynn.com Change-Id: Ie11ab68267438ea9c669c809985c0c2d7578280e --- M src/mainboard/ocp/tiogapass/Kconfig M src/mainboard/ocp/tiogapass/Makefile.inc A src/mainboard/ocp/tiogapass/ipmi.c A src/mainboard/ocp/tiogapass/ipmi.h M src/mainboard/ocp/tiogapass/ramstage.c 5 files changed, 76 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/40524/3
Hello build bot (Jenkins), Andrey Petrov, Patrick Georgi, Martin Roth, Jonathan Zhang, David Hendricks, Jingle Hsu, Morgan Jang,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40524
to look at the new patch set (#4).
Change subject: mb/ocp/tiogapass: Populate SMBIOS data and set the read PPIN to BMC ......................................................................
mb/ocp/tiogapass: Populate SMBIOS data and set the read PPIN to BMC
1. Populate SMBIOS data from OCP_DMI driver read from FRU 2. Set the read PPIN MSR for CPU0 and CPU1 to BMC.
Tested on OCP Tioga Pass.
Signed-off-by: Johnny Lin johnny_lin@wiwynn.com Change-Id: Ie11ab68267438ea9c669c809985c0c2d7578280e --- M src/mainboard/ocp/tiogapass/Kconfig M src/mainboard/ocp/tiogapass/Makefile.inc A src/mainboard/ocp/tiogapass/ipmi.c A src/mainboard/ocp/tiogapass/ipmi.h M src/mainboard/ocp/tiogapass/ramstage.c 5 files changed, 76 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/40524/4
Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40524 )
Change subject: mb/ocp/tiogapass: Populate SMBIOS data and set the read PPIN to BMC ......................................................................
Patch Set 4:
(3 comments)
https://review.coreboot.org/c/coreboot/+/40524/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/40524/2//COMMIT_MSG@14 PS2, Line 14:
Please remove the blank line.
Done
https://review.coreboot.org/c/coreboot/+/40524/2/src/mainboard/ocp/tiogapass... File src/mainboard/ocp/tiogapass/ipmi.h:
https://review.coreboot.org/c/coreboot/+/40524/2/src/mainboard/ocp/tiogapass... PS2, Line 16: uint32_t CPU0lo;
coreboot prefers lowercase variable names.
Done
https://review.coreboot.org/c/coreboot/+/40524/2/src/mainboard/ocp/tiogapass... File src/mainboard/ocp/tiogapass/ipmi.c:
https://review.coreboot.org/c/coreboot/+/40524/2/src/mainboard/ocp/tiogapass... PS2, Line 23: printk(BIOS_INFO, "IPMI Set PPIN done.\n");
The current style suggests, it’s a debug message. For BIOS_INFO, please improve the wording.
Changed to BIOS_DEBUG.
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40524 )
Change subject: mb/ocp/tiogapass: Populate SMBIOS data and set the read PPIN to BMC ......................................................................
Patch Set 6:
(3 comments)
https://review.coreboot.org/c/coreboot/+/40524/6/src/mainboard/ocp/tiogapass... File src/mainboard/ocp/tiogapass/Kconfig:
https://review.coreboot.org/c/coreboot/+/40524/6/src/mainboard/ocp/tiogapass... PS6, Line 26: select OCP_DMI Let's put this in alphabetical order.
https://review.coreboot.org/c/coreboot/+/40524/6/src/mainboard/ocp/tiogapass... File src/mainboard/ocp/tiogapass/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/40524/6/src/mainboard/ocp/tiogapass... PS6, Line 18: ramstage-y += ipmi.c line 17, 18 can be in same line.
https://review.coreboot.org/c/coreboot/+/40524/6/src/mainboard/ocp/tiogapass... File src/mainboard/ocp/tiogapass/ramstage.c:
https://review.coreboot.org/c/coreboot/+/40524/6/src/mainboard/ocp/tiogapass... PS6, Line 20: #include <drivers/ipmi/ipmi_ops.h> alphabetical order please.
Hello build bot (Jenkins), Andrey Petrov, Patrick Georgi, Martin Roth, Jonathan Zhang, David Hendricks, Jingle Hsu, Morgan Jang,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40524
to look at the new patch set (#7).
Change subject: mb/ocp/tiogapass: Populate SMBIOS data and set the read PPIN to BMC ......................................................................
mb/ocp/tiogapass: Populate SMBIOS data and set the read PPIN to BMC
1. Populate SMBIOS data from OCP_DMI driver read from FRU 2. Set the read PPIN MSR for CPU0 and CPU1 to BMC.
Tested on OCP Tioga Pass.
Signed-off-by: Johnny Lin johnny_lin@wiwynn.com Change-Id: Ie11ab68267438ea9c669c809985c0c2d7578280e --- M src/mainboard/ocp/tiogapass/Kconfig M src/mainboard/ocp/tiogapass/Makefile.inc A src/mainboard/ocp/tiogapass/ipmi.c A src/mainboard/ocp/tiogapass/ipmi.h M src/mainboard/ocp/tiogapass/ramstage.c 5 files changed, 77 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/40524/7
Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40524 )
Change subject: mb/ocp/tiogapass: Populate SMBIOS data and set the read PPIN to BMC ......................................................................
Patch Set 7:
(3 comments)
https://review.coreboot.org/c/coreboot/+/40524/6/src/mainboard/ocp/tiogapass... File src/mainboard/ocp/tiogapass/Kconfig:
https://review.coreboot.org/c/coreboot/+/40524/6/src/mainboard/ocp/tiogapass... PS6, Line 26: select OCP_DMI
Let's put this in alphabetical order.
Done
https://review.coreboot.org/c/coreboot/+/40524/6/src/mainboard/ocp/tiogapass... File src/mainboard/ocp/tiogapass/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/40524/6/src/mainboard/ocp/tiogapass... PS6, Line 18: ramstage-y += ipmi.c
line 17, 18 can be in same line.
Done
https://review.coreboot.org/c/coreboot/+/40524/6/src/mainboard/ocp/tiogapass... File src/mainboard/ocp/tiogapass/ramstage.c:
https://review.coreboot.org/c/coreboot/+/40524/6/src/mainboard/ocp/tiogapass... PS6, Line 20: #include <drivers/ipmi/ipmi_ops.h>
alphabetical order please.
Done
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40524 )
Change subject: mb/ocp/tiogapass: Populate SMBIOS data and set the read PPIN to BMC ......................................................................
Patch Set 10: Code-Review+1
Hello build bot (Jenkins), Andrey Petrov, Patrick Georgi, Martin Roth, Jonathan Zhang, David Hendricks, Jingle Hsu, Morgan Jang,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40524
to look at the new patch set (#11).
Change subject: mb/ocp/tiogapass: Populate SMBIOS data and set the read PPIN to BMC ......................................................................
mb/ocp/tiogapass: Populate SMBIOS data and set the read PPIN to BMC
1. Populate SMBIOS data from OCP_DMI driver read from FRU 2. Set the read PPIN MSR for CPU0 and CPU1 to BMC, selecting PARALLEL_MP_AP_WORK to enable OCP DMI driver to read remote socket PPIN.
Tested on OCP Tioga Pass.
Signed-off-by: Johnny Lin johnny_lin@wiwynn.com Change-Id: Ie11ab68267438ea9c669c809985c0c2d7578280e --- M src/mainboard/ocp/tiogapass/Kconfig M src/mainboard/ocp/tiogapass/Makefile.inc A src/mainboard/ocp/tiogapass/ipmi.c A src/mainboard/ocp/tiogapass/ipmi.h M src/mainboard/ocp/tiogapass/ramstage.c 5 files changed, 77 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/40524/11
Hello build bot (Jenkins), Andrey Petrov, Patrick Georgi, Martin Roth, Jonathan Zhang, David Hendricks, Jingle Hsu, Morgan Jang,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40524
to look at the new patch set (#12).
Change subject: mb/ocp/tiogapass: Populate SMBIOS data and set the read PPIN to BMC ......................................................................
mb/ocp/tiogapass: Populate SMBIOS data and set the read PPIN to BMC
1. Populate SMBIOS data from OCP_DMI driver read from FRU 2. Set the read PPIN MSR for CPU0 and CPU1 to BMC, selecting PARALLEL_MP_AP_WORK to enable OCP DMI driver to read remote socket PPIN.
Tested on OCP Tioga Pass.
Signed-off-by: Johnny Lin johnny_lin@wiwynn.com Change-Id: Ie11ab68267438ea9c669c809985c0c2d7578280e --- M src/mainboard/ocp/tiogapass/Kconfig M src/mainboard/ocp/tiogapass/Makefile.inc A src/mainboard/ocp/tiogapass/ipmi.c A src/mainboard/ocp/tiogapass/ipmi.h M src/mainboard/ocp/tiogapass/ramstage.c 5 files changed, 79 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/40524/12
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40524 )
Change subject: mb/ocp/tiogapass: Populate SMBIOS data and set the read PPIN to BMC ......................................................................
Patch Set 14: Code-Review+1
Hello build bot (Jenkins), Andrey Petrov, Patrick Georgi, Martin Roth, Jonathan Zhang, David Hendricks, Jingle Hsu, Morgan Jang,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40524
to look at the new patch set (#20).
Change subject: mb/ocp/tiogapass: Populate SMBIOS data and set the read PPIN to BMC ......................................................................
mb/ocp/tiogapass: Populate SMBIOS data and set the read PPIN to BMC
1. Populate SMBIOS data from OCP_DMI driver read from FRU 2. Set the read PPIN MSR for CPU0 and CPU1 to BMC, selecting PARALLEL_MP_AP_WORK to enable OCP DMI driver to read remote socket PPIN.
Tested on OCP Tioga Pass.
Signed-off-by: Johnny Lin johnny_lin@wiwynn.com Change-Id: Ie11ab68267438ea9c669c809985c0c2d7578280e --- M src/mainboard/ocp/tiogapass/Kconfig M src/mainboard/ocp/tiogapass/Makefile.inc A src/mainboard/ocp/tiogapass/ipmi.c A src/mainboard/ocp/tiogapass/ipmi.h M src/mainboard/ocp/tiogapass/ramstage.c 5 files changed, 94 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/40524/20
Hello build bot (Jenkins), Andrey Petrov, Patrick Georgi, Martin Roth, Jonathan Zhang, David Hendricks, Jingle Hsu, Morgan Jang,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40524
to look at the new patch set (#22).
Change subject: mb/ocp/tiogapass: Populate SMBIOS data and set the read PPIN to BMC ......................................................................
mb/ocp/tiogapass: Populate SMBIOS data and set the read PPIN to BMC
1. Populate SMBIOS data from OCP_DMI driver read from FRU 2. Set the read PPIN MSR for CPU0 and CPU1 to BMC, selecting PARALLEL_MP_AP_WORK to enable OCP DMI driver to read remote socket PPIN.
Tested on OCP Tioga Pass.
Signed-off-by: Johnny Lin johnny_lin@wiwynn.com Change-Id: Ie11ab68267438ea9c669c809985c0c2d7578280e --- M src/mainboard/ocp/tiogapass/Kconfig M src/mainboard/ocp/tiogapass/Makefile.inc A src/mainboard/ocp/tiogapass/ipmi.c A src/mainboard/ocp/tiogapass/ipmi.h M src/mainboard/ocp/tiogapass/ramstage.c 5 files changed, 94 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/40524/22
Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40524 )
Change subject: mb/ocp/tiogapass: Populate SMBIOS data and set the read PPIN to BMC ......................................................................
Patch Set 22:
If the OEM set PPIN command can be moved to CB:41232, I will move it there once CB:41232 review is done.
Hello build bot (Jenkins), Andrey Petrov, Patrick Georgi, Martin Roth, Jonathan Zhang, David Hendricks, Jingle Hsu, Morgan Jang,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40524
to look at the new patch set (#26).
Change subject: mb/ocp/tiogapass: Populate SMBIOS data and set the read PPIN to BMC ......................................................................
mb/ocp/tiogapass: Populate SMBIOS data and set the read PPIN to BMC
1. Populate SMBIOS data from OCP_DMI driver read from FRU 2. Set the read PPIN MSR for CPU0 and CPU1 to BMC, selecting PARALLEL_MP_AP_WORK to enable OCP DMI driver to read remote socket PPIN.
Tested on OCP Tioga Pass.
Signed-off-by: Johnny Lin johnny_lin@wiwynn.com Change-Id: Ie11ab68267438ea9c669c809985c0c2d7578280e --- M src/mainboard/ocp/tiogapass/Kconfig M src/mainboard/ocp/tiogapass/Makefile.inc A src/mainboard/ocp/tiogapass/ipmi.c A src/mainboard/ocp/tiogapass/ipmi.h M src/mainboard/ocp/tiogapass/ramstage.c 5 files changed, 92 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/40524/26
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40524 )
Change subject: mb/ocp/tiogapass: Populate SMBIOS data and set the read PPIN to BMC ......................................................................
Patch Set 28: Code-Review+2
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40524 )
Change subject: mb/ocp/tiogapass: Populate SMBIOS data and set the read PPIN to BMC ......................................................................
mb/ocp/tiogapass: Populate SMBIOS data and set the read PPIN to BMC
1. Populate SMBIOS data from OCP_DMI driver read from FRU 2. Set the read PPIN MSR for CPU0 and CPU1 to BMC, selecting PARALLEL_MP_AP_WORK to enable OCP DMI driver to read remote socket PPIN.
Tested on OCP Tioga Pass.
Signed-off-by: Johnny Lin johnny_lin@wiwynn.com Change-Id: Ie11ab68267438ea9c669c809985c0c2d7578280e Reviewed-on: https://review.coreboot.org/c/coreboot/+/40524 Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/ocp/tiogapass/Kconfig M src/mainboard/ocp/tiogapass/Makefile.inc A src/mainboard/ocp/tiogapass/ipmi.c A src/mainboard/ocp/tiogapass/ipmi.h M src/mainboard/ocp/tiogapass/ramstage.c 5 files changed, 92 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/mainboard/ocp/tiogapass/Kconfig b/src/mainboard/ocp/tiogapass/Kconfig index 421d400..79dafa7 100644 --- a/src/mainboard/ocp/tiogapass/Kconfig +++ b/src/mainboard/ocp/tiogapass/Kconfig @@ -6,8 +6,10 @@ def_bool y select BOARD_ROMSIZE_KB_32768 select HAVE_ACPI_TABLES - select MAINBOARD_USES_FSP2_0 select IPMI_KCS + select MAINBOARD_USES_FSP2_0 + select OCP_DMI + select PARALLEL_MP_AP_WORK select SOC_INTEL_SKYLAKE_SP select SUPERIO_ASPEED_AST2400
diff --git a/src/mainboard/ocp/tiogapass/Makefile.inc b/src/mainboard/ocp/tiogapass/Makefile.inc index ca4e463..bb4a86b 100644 --- a/src/mainboard/ocp/tiogapass/Makefile.inc +++ b/src/mainboard/ocp/tiogapass/Makefile.inc @@ -1,7 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-or-later
bootblock-y += bootblock.c -ramstage-y += ramstage.c +ramstage-y += ramstage.c ipmi.c
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include CPPFLAGS_common += -I$(CONFIG_FSP_HEADER_PATH) diff --git a/src/mainboard/ocp/tiogapass/ipmi.c b/src/mainboard/ocp/tiogapass/ipmi.c new file mode 100644 index 0000000..aa50688 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/ipmi.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <drivers/ipmi/ipmi_kcs.h> + +#include "ipmi.h" + +void ipmi_set_ppin(struct ppin_req *req) +{ + int ret; + struct ipmi_rsp rsp; + + ret = ipmi_kcs_message(CONFIG_BMC_KCS_BASE, IPMI_NETFN_OEM, 0x0, IPMI_OEM_SET_PPIN, + (const unsigned char *) req, sizeof(*req), + (unsigned char *) &rsp, sizeof(rsp)); + + if (ret < sizeof(struct ipmi_rsp) || rsp.completion_code) { + printk(BIOS_ERR, "IPMI: %s command failed (ret=%d resp=0x%x)\n", + __func__, ret, rsp.completion_code); + return; + } + printk(BIOS_DEBUG, "IPMI Set PPIN to BMC done.\n"); +} diff --git a/src/mainboard/ocp/tiogapass/ipmi.h b/src/mainboard/ocp/tiogapass/ipmi.h new file mode 100644 index 0000000..3d2723f --- /dev/null +++ b/src/mainboard/ocp/tiogapass/ipmi.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef TIOGAPASS_IPMI_H +#define TIOGAPASS_IPMI_H +#include <types.h> + +#define IPMI_NETFN_OEM 0x30 +#define IPMI_OEM_SET_PPIN 0x77 + +/* PPIN for 2 CPU IPMI request */ +struct ppin_req { + uint32_t cpu0_lo; + uint32_t cpu0_hi; + uint32_t cpu1_lo; + uint32_t cpu1_hi; +} __packed; +/* Send CPU0 and CPU1 PPIN to BMC */ +void ipmi_set_ppin(struct ppin_req *req); +#endif diff --git a/src/mainboard/ocp/tiogapass/ramstage.c b/src/mainboard/ocp/tiogapass/ramstage.c index 82b260d..f02667b 100644 --- a/src/mainboard/ocp/tiogapass/ramstage.c +++ b/src/mainboard/ocp/tiogapass/ramstage.c @@ -1,9 +1,17 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ + #include <soc/ramstage.h> #include <bootstate.h> +#include <drivers/ipmi/ipmi_ops.h> +#include <drivers/ocp/dmi/ocp_dmi.h> #include <gpio.h> +#include <soc/ramstage.h> #include <soc/lewisburg_pch_gpio_defs.h>
+#include "ipmi.h" + +extern struct fru_info_str fru_strings; + void mainboard_silicon_init_params(FSPS_UPD *params) { } @@ -14,4 +22,42 @@ gpio_output(GPP_B20, 0); }
+ +static void tp_oem_smbios_strings(struct device *dev, struct smbios_type11 *t) +{ + /* OEM string 1 to 6 */ + ocp_oem_smbios_strings(dev, t); + + /* OEM string 7 */ + if (fru_strings.board_info.custom_count > 1 && + *(fru_strings.board_info.board_custom + 1) != NULL) + t->count = smbios_add_oem_string(t->eos, + *(fru_strings.board_info.board_custom + 1)); + else + t->count = smbios_add_oem_string(t->eos, TBF); +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->get_smbios_strings = tp_oem_smbios_strings, + read_fru_areas(CONFIG_BMC_KCS_BASE, CONFIG_FRU_DEVICE_ID, 0, &fru_strings); +} + +static void mainboard_final(void *chip_info) +{ + struct ppin_req req; + + req.cpu0_lo = xeon_sp_ppin[0].lo; + req.cpu0_hi = xeon_sp_ppin[0].hi; + req.cpu1_lo = xeon_sp_ppin[1].lo; + req.cpu1_hi = xeon_sp_ppin[1].hi; + /* Set PPIN to BMC */ + ipmi_set_ppin(&req); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, + .final = mainboard_final, +}; + BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, pull_post_complete_pin, NULL);
-
Angel Pons (Code Review) -
Johnny Lin (Code Review)
-
Jonathan Zhang (Code Review)
-
Paul Menzel (Code Review)