Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45041 )
Change subject: soc/intel/xeon_sp: Select CPU_INTEL_COMMON ......................................................................
soc/intel/xeon_sp: Select CPU_INTEL_COMMON
This is an intermediate step to have SOC_INTEL_COMMON_BLOCK_CPU select CPU_INTEL_COMMON directly, to avoid dependency problems.
Change-Id: I565e75869be730e7c2fe7114b829941bc9890e6c Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/xeon_sp/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/45041/1
diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index a4274df..31d12fc 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -31,6 +31,7 @@ select ARCH_VERSTAGE_X86_32 select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES + select CPU_INTEL_COMMON select SOC_INTEL_COMMON select SOC_INTEL_COMMON_RESET select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45041 )
Change subject: soc/intel/xeon_sp: Select CPU_INTEL_COMMON ......................................................................
Patch Set 1:
is VMX supported ?
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45041 )
Change subject: soc/intel/xeon_sp: Select CPU_INTEL_COMMON ......................................................................
Patch Set 1:
Patch Set 1:
is VMX supported ?
Yes. The CPX-SP has a VmxEnable UPD parameter that can be turned on.
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45041 )
Change subject: soc/intel/xeon_sp: Select CPU_INTEL_COMMON ......................................................................
Patch Set 1:
Hi Angel, did you try this on DeltaLake EVT server?
Rocky, CPU_INTEL_COMMON_SMM is selected once CPU_INTEL_COMMON is selected.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45041 )
Change subject: soc/intel/xeon_sp: Select CPU_INTEL_COMMON ......................................................................
Patch Set 1:
Patch Set 1:
Hi Angel, did you try this on DeltaLake EVT server?
Rocky, CPU_INTEL_COMMON_SMM is selected once CPU_INTEL_COMMON is selected.
I forgot to add it to the commit message, but both Tioga Pass and Delta Lake remain unchanged when building with BUILD_TIMELESS=1. Without adding the config into the coreboot.rom, the resulting timeless coreboot.rom before and after applying this commit are identical.
Hello build bot (Jenkins), Anjaneya "Reddy" Chagam, Jonathan Zhang, Rocky Phagura, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45041
to look at the new patch set (#2).
Change subject: soc/intel/xeon_sp: Select CPU_INTEL_COMMON ......................................................................
soc/intel/xeon_sp: Select CPU_INTEL_COMMON
This is an intermediate step to have SOC_INTEL_COMMON_BLOCK_CPU select CPU_INTEL_COMMON directly, to avoid dependency problems.
Tested with BUILD_TIMELESS=1: Without including the config file in the coreboot.rom, both OCP Tioga Pass and Delta Lake remain identical.
Change-Id: I565e75869be730e7c2fe7114b829941bc9890e6c Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/xeon_sp/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/45041/2
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45041 )
Change subject: soc/intel/xeon_sp: Select CPU_INTEL_COMMON ......................................................................
Patch Set 2: Code-Review+2
Rocky Phagura has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45041 )
Change subject: soc/intel/xeon_sp: Select CPU_INTEL_COMMON ......................................................................
Patch Set 2:
So I gave this a quick test. Added a function call to set_vmx_and_lock in cpx_init_cpus() and turned on CPU_INTEL_COMMON in Kconfig along with the other SMM features I've been testing:
select CPU_INTEL_COMMON_SMM select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_PMC select ACPI_INTEL_HARDWARE_SLEEP_VALUES select SMM_TSEG select HAVE_SMI_HANDLER select X86_SMM_LOADER_VERSION2 select REG_SCRIPT
And the Coreboot log shows this (I added some print debug messages)
set_vmx_and_lock enter set_feature_ctrl_vmx enter VMX status: enabled set_feature_ctrl_lock enter IA32_FEATURE_CONTROL status: locked set_vmx_and_lock exit
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45041 )
Change subject: soc/intel/xeon_sp: Select CPU_INTEL_COMMON ......................................................................
soc/intel/xeon_sp: Select CPU_INTEL_COMMON
This is an intermediate step to have SOC_INTEL_COMMON_BLOCK_CPU select CPU_INTEL_COMMON directly, to avoid dependency problems.
Tested with BUILD_TIMELESS=1: Without including the config file in the coreboot.rom, both OCP Tioga Pass and Delta Lake remain identical.
Change-Id: I565e75869be730e7c2fe7114b829941bc9890e6c Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/45041 Reviewed-by: Jonathan Zhang jonzhang@fb.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/xeon_sp/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Jonathan Zhang: Looks good to me, approved
diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index a4274df..31d12fc 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -31,6 +31,7 @@ select ARCH_VERSTAGE_X86_32 select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES + select CPU_INTEL_COMMON select SOC_INTEL_COMMON select SOC_INTEL_COMMON_RESET select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS
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Angel Pons (Code Review) -
HAOUAS Elyes (Code Review)
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Jonathan Zhang (Code Review)
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Patrick Georgi (Code Review)
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Rocky Phagura (Code Review)