Change in coreboot[master]: mb/google/brya: Enable display and DSP audio UPD

[Sugnan Prabhu S (Code Review)]

Attention is currently required from: Furquan Shaikh, Paul Menzel, Subrata Banik, Sathya Prakash M R, Tim Wawrzynczak.
Sugnan Prabhu S has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51510 )

Change subject: mb/google/brya: Enable display and DSP audio UPD
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Patch Set 4:

(1 comment)

File src/mainboard/google/brya/variants/baseboard/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/51510/comment/3ac6c753_a9ca0866 
PS2, Line 63: register "PchHdaAudioLinkHdaEnable" = "0"
            : 	register "PchHdaAudioLinkDmicEnable[0]" = "1"
            : 	register "PchHdaAudioLinkDmicEnable[1]" = "1"
            : 	register "PchHdaAudioLinkSspEnable[0]" = "1"
            : 	register "PchHdaAudioLinkSspEnable[2]" = "1
> I would like to see an explanation of why these configs are dropped and set to 0.

As Coreboot already takes care of defaulting the config values to 0, it will not be useful setting any config to zero, hence dropped the values which were been setting to 0.
Need to dig deeper to understand why setting the PchHdaAudioLinkSspEnable to 0 made it work. This is the main change, any further changes will be part of overridetree.cb and will be pushed as separate patch.