Attention is currently required from: Ashish Kumar Mishra, Bora Guvendik.
Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80334?usp=email )
Change subject: brox: Handle GPI_INT pin value lower to GPI_WAKE ......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1: Thank you Ashish for debugging this issue!
I am a bit confused... are you saying that this originally was happening because the EC INT pin was set to GPP_D0 and the EC WAKE pin was set to GPP_D1? But we were also seeing this issue when the pins were swapped originally (a config mistake corrected by https://review.coreboot.org/c/coreboot/+/79886). We were also seeing the same conflict behavior between cros_ec_lpcs and the iadma64 driver at that point too, except it was happening on IRQ #45 instead (as you can see in the dmesg output in https://issuetracker.google.com/319129926#comment1). Was wondering if you know why we were seeing the same issue if the WAKE pin (GPP_D0 at the time) was lower than the INT pin (GPP_D1 at the time) at that point?