Marc Jones (marc@marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18440
-gerrit
commit ce9320f4f2ba8b165c27093811980e0460361159 Author: Marshall Dawson marshalldawson3rd@gmail.com Date: Sun Jan 29 17:22:36 2017 -0700
amd/pi/hudson: Move BITn definitions to header file
In preparation for subsequent patches, move definitions from a .c file to hudson.h. Also change the method for generating the values from LSH and update some existing defintions to use BINn.
Orignial-Signed-off-by: Marshall Dawson marshalldawson3rd@gmail.com Original-Reviewed-by: Marc Jones marcj303@gmail.com (cherry picked from commit f403d12b49985ee9d9b339a6659b60ef1560519c)
Change-Id: I24105bf75263236dbdbc2666f03033069d1d36d2 Signed-off-by: Marc Jones marcj303@gmail.com --- src/southbridge/amd/pi/hudson/hudson.h | 99 +++++++++++++++++++++++----------- src/southbridge/amd/pi/hudson/sm.c | 35 ------------ 2 files changed, 67 insertions(+), 67 deletions(-)
diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h index 23d9b31..7835f68 100644 --- a/src/southbridge/amd/pi/hudson/hudson.h +++ b/src/southbridge/amd/pi/hudson/hudson.h @@ -21,6 +21,41 @@ #include <device/device.h> #include "chip.h"
+#ifndef BIT0 +#define BIT0 0x00000001 +#define BIT1 0x00000002 +#define BIT2 0x00000004 +#define BIT3 0x00000008 +#define BIT4 0x00000010 +#define BIT5 0x00000020 +#define BIT6 0x00000040 +#define BIT7 0x00000080 +#define BIT8 0x00000100 +#define BIT9 0x00000200 +#define BIT10 0x00000400 +#define BIT11 0x00000800 +#define BIT12 0x00001000 +#define BIT13 0x00002000 +#define BIT14 0x00004000 +#define BIT15 0x00008000 +#define BIT16 0x00010000 +#define BIT17 0x00020000 +#define BIT18 0x00040000 +#define BIT19 0x00080000 +#define BIT20 0x00100000 +#define BIT21 0x00200000 +#define BIT22 0x00400000 +#define BIT23 0x00800000 +#define BIT24 0x01000000 +#define BIT25 0x02000000 +#define BIT26 0x04000000 +#define BIT27 0x08000000 +#define BIT28 0x10000000 +#define BIT29 0x20000000 +#define BIT30 0x40000000 +#define BIT31 0x80000000 +#endif + /* Power management index/data registers */ #define BIOSRAM_INDEX 0xcd4 #define BIOSRAM_DATA 0xcd5 @@ -52,38 +87,38 @@ #define SPI_BASE_ADDRESS 0xFEC10000
#define LPC_IO_PORT_DECODE_ENABLE 0x44 -#define DECODE_ENABLE_PARALLEL_PORT0 (1 << 0) -#define DECODE_ENABLE_PARALLEL_PORT1 (1 << 1) -#define DECODE_ENABLE_PARALLEL_PORT2 (1 << 2) -#define DECODE_ENABLE_PARALLEL_PORT3 (1 << 3) -#define DECODE_ENABLE_PARALLEL_PORT4 (1 << 4) -#define DECODE_ENABLE_PARALLEL_PORT5 (1 << 5) -#define DECODE_ENABLE_SERIAL_PORT0 (1 << 6) -#define DECODE_ENABLE_SERIAL_PORT1 (1 << 7) -#define DECODE_ENABLE_SERIAL_PORT2 (1 << 8) -#define DECODE_ENABLE_SERIAL_PORT3 (1 << 9) -#define DECODE_ENABLE_SERIAL_PORT4 (1 << 10) -#define DECODE_ENABLE_SERIAL_PORT5 (1 << 11) -#define DECODE_ENABLE_SERIAL_PORT6 (1 << 12) -#define DECODE_ENABLE_SERIAL_PORT7 (1 << 13) -#define DECODE_ENABLE_AUDIO_PORT0 (1 << 14) -#define DECODE_ENABLE_AUDIO_PORT1 (1 << 15) -#define DECODE_ENABLE_AUDIO_PORT2 (1 << 16) -#define DECODE_ENABLE_AUDIO_PORT3 (1 << 17) -#define DECODE_ENABLE_MIDI_PORT0 (1 << 18) -#define DECODE_ENABLE_MIDI_PORT1 (1 << 19) -#define DECODE_ENABLE_MIDI_PORT2 (1 << 20) -#define DECODE_ENABLE_MIDI_PORT3 (1 << 21) -#define DECODE_ENABLE_MSS_PORT0 (1 << 22) -#define DECODE_ENABLE_MSS_PORT1 (1 << 23) -#define DECODE_ENABLE_MSS_PORT2 (1 << 24) -#define DECODE_ENABLE_MSS_PORT3 (1 << 25) -#define DECODE_ENABLE_FDC_PORT0 (1 << 26) -#define DECODE_ENABLE_FDC_PORT1 (1 << 27) -#define DECODE_ENABLE_GAME_PORT (1 << 28) -#define DECODE_ENABLE_KBC_PORT (1 << 29) -#define DECODE_ENABLE_ACPIUC_PORT (1 << 30) -#define DECODE_ENABLE_ADLIB_PORT (1 << 31) +#define DECODE_ENABLE_PARALLEL_PORT0 (BIT0) +#define DECODE_ENABLE_PARALLEL_PORT1 (BIT1) +#define DECODE_ENABLE_PARALLEL_PORT2 (BIT2) +#define DECODE_ENABLE_PARALLEL_PORT3 (BIT3) +#define DECODE_ENABLE_PARALLEL_PORT4 (BIT4) +#define DECODE_ENABLE_PARALLEL_PORT5 (BIT5) +#define DECODE_ENABLE_SERIAL_PORT0 (BIT6) +#define DECODE_ENABLE_SERIAL_PORT1 (BIT7) +#define DECODE_ENABLE_SERIAL_PORT2 (BIT8) +#define DECODE_ENABLE_SERIAL_PORT3 (BIT9) +#define DECODE_ENABLE_SERIAL_PORT4 (BIT10) +#define DECODE_ENABLE_SERIAL_PORT5 (BIT11) +#define DECODE_ENABLE_SERIAL_PORT6 (BIT12) +#define DECODE_ENABLE_SERIAL_PORT7 (BIT13) +#define DECODE_ENABLE_AUDIO_PORT0 (BIT14) +#define DECODE_ENABLE_AUDIO_PORT1 (BIT15) +#define DECODE_ENABLE_AUDIO_PORT2 (BIT16) +#define DECODE_ENABLE_AUDIO_PORT3 (BIT17) +#define DECODE_ENABLE_MIDI_PORT0 (BIT18) +#define DECODE_ENABLE_MIDI_PORT1 (BIT19) +#define DECODE_ENABLE_MIDI_PORT2 (BIT20) +#define DECODE_ENABLE_MIDI_PORT3 (BIT21) +#define DECODE_ENABLE_MSS_PORT0 (BIT22) +#define DECODE_ENABLE_MSS_PORT1 (BIT23) +#define DECODE_ENABLE_MSS_PORT2 (BIT24) +#define DECODE_ENABLE_MSS_PORT3 (BIT25) +#define DECODE_ENABLE_FDC_PORT0 (BIT26) +#define DECODE_ENABLE_FDC_PORT1 (BIT27) +#define DECODE_ENABLE_GAME_PORT (BIT28) +#define DECODE_ENABLE_KBC_PORT (BIT29) +#define DECODE_ENABLE_ACPIUC_PORT (BIT30) +#define DECODE_ENABLE_ADLIB_PORT (BIT31)
static inline int hudson_sata_enable(void) { diff --git a/src/southbridge/amd/pi/hudson/sm.c b/src/southbridge/amd/pi/hudson/sm.c index 74367a7..db29d10 100644 --- a/src/southbridge/amd/pi/hudson/sm.c +++ b/src/southbridge/amd/pi/hudson/sm.c @@ -36,41 +36,6 @@ #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif
-#define BIT0 (1 << 0) -#define BIT1 (1 << 1) -#define BIT2 (1 << 2) -#define BIT3 (1 << 3) -#define BIT4 (1 << 4) -#define BIT5 (1 << 5) -#define BIT6 (1 << 6) -#define BIT7 (1 << 7) - -#define BIT8 (1 << 8 ) -#define BIT9 (1 << 9 ) -#define BIT10 (1 << 10) -#define BIT11 (1 << 11) -#define BIT12 (1 << 12) -#define BIT13 (1 << 13) -#define BIT14 (1 << 14) -#define BIT15 (1 << 15) - -#define BIT16 (1 << 16) -#define BIT17 (1 << 17) -#define BIT18 (1 << 18) -#define BIT19 (1 << 19) -#define BIT20 (1 << 20) -#define BIT21 (1 << 21) -#define BIT22 (1 << 22) -#define BIT23 (1 << 23) -#define BIT24 (1 << 24) -#define BIT25 (1 << 25) -#define BIT26 (1 << 26) -#define BIT27 (1 << 27) -#define BIT28 (1 << 28) -#define BIT29 (1 << 29) -#define BIT30 (1 << 30) -#define BIT31 (1 << 31) - /* * HUDSON enables all USB controllers by default in SMBUS Control. * HUDSON enables SATA by default in SMBUS Control.
-
Marc Jones