Change in ...coreboot[master]: cpu/x86/mtrr: Fix sign overflow

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30502 )

Change subject: cpu/x86/mtrr: Fix sign overflow
......................................................................

cpu/x86/mtrr: Fix sign overflow

Use unsigned long to prevent sign overflow.
Fixes wrong MTRRs settings on x86_64 romstage.

Signed-off-by: Patrick Rudolph <[e-mail]>
Change-Id: I71b61a45becc17bf60a619e4131864c82a16b0d1
Reviewed-on: https://review.coreboot.org/c/30502
Tested-by: build bot (Jenkins) <[e-mail]>
Reviewed-by: Angel Pons <[e-mail]>
Reviewed-by: Paul Menzel <[e-mail]>
---
M src/include/cpu/x86/mtrr.h
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Paul Menzel: Looks good to me, but someone else must approve
  Angel Pons: Looks good to me, approved



diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index eb7d78d..0398a2e 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -150,7 +150,7 @@
 #define _ALIGN_DOWN_POW2(x)	((x) & ~_POW2_MASK(x))
 
 /* Calculate `4GiB - x` (e.g. absolute address for offset from 4GiB) */
-#define _FROM_4G_TOP(x) (((1 << 20) - ((x) >> 12)) << 12)
+#define _FROM_4G_TOP(x) (((1UL << 20) - ((x) >> 12)) << 12)
 
 /* At the end of romstage, low RAM 0..CACHE_TM_RAMTOP may be set
  * as write-back cacheable to speed up ramstage decompression.

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I71b61a45becc17bf60a619e4131864c82a16b0d1
Gerrit-Change-Number: 30502
Gerrit-PatchSet: 4
Gerrit-Owner: Patrick Rudolph <[e-mail]>
Gerrit-Reviewer: Angel Pons <[e-mail]>
Gerrit-Reviewer: Arthur Heymans <[e-mail]>
Gerrit-Reviewer: Patrick Georgi <[e-mail]>
Gerrit-Reviewer: Patrick Rudolph <[e-mail]>
Gerrit-Reviewer: Paul Menzel <[e-mail]>
Gerrit-Reviewer: build bot (Jenkins) <[e-mail]>
Gerrit-MessageType: merged