[XS] Change in coreboot[main]: Revert "UPSTREAM: soc/intel/pantherlake: Update PlatformDebugOption t...

[Subrata Banik (Code Review)]

Attention is currently required from: Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Pranava Y N.

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86105?usp=email )

Change subject: Revert "UPSTREAM: soc/intel/pantherlake: Update PlatformDebugOption to Trace Ready"
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Revert "UPSTREAM: soc/intel/pantherlake: Update PlatformDebugOption to Trace Ready"

This default configuration caused a problem where USB devices connected
behind a powered hub and/or Servo v4.1 were not detected.

Reverting this change restores the previous behavior where Trace Hub
and DCI are disabled by default, resolving the USB detection issue.

BUG=b:384453901
TEST=Able to boot google/fatcat using USB storage behind servo v4.1

This reverts commit 1ed186fbff84386e0196dd30dd7bc89b8fec2cec.

Change-Id: I1a0f66d7ddf84622820f82c559d7d6b846ba3a7d
Signed-off-by: Subrata Banik 
---
M src/soc/intel/pantherlake/Kconfig
1 file changed, 0 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/86105/1

diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index 4f6f658..dde401b 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -95,7 +95,6 @@
    select SOC_INTEL_CSE_LITE_PSR if MAINBOARD_HAS_CHROMEOS && SOC_INTEL_CSE_LITE_SKU
    select SOC_INTEL_CSE_SEND_EOP_LATE if !MAINBOARD_HAS_CHROMEOS
    select SOC_INTEL_CSE_SET_EOP
-	select SOC_INTEL_DEBUG_CONSENT # TODO: Remove the safe setting for ES SoC
    select SOC_INTEL_GFX_NON_PREFETCHABLE_MMIO
    select SOC_INTEL_IOE_DIE_SUPPORT
    select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION