Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37334 )
Change subject: Drop ROMCC code and header guards ......................................................................
Drop ROMCC code and header guards
Change-Id: I730f80afd8aad250f26534435aec24bea75a849c Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/arch/x86/assembly_entry.S M src/arch/x86/c_start.S M src/arch/x86/include/arch/acpi.h D src/arch/x86/include/arch/bootblock_romcc.h M src/arch/x86/include/arch/cpu.h M src/arch/x86/include/arch/hlt.h M src/arch/x86/include/arch/io.h M src/arch/x86/include/arch/mmio.h D src/arch/x86/include/arch/pci_mmio_cfg_romcc.h M src/arch/x86/include/arch/pci_ops.h M src/commonlib/include/commonlib/cbfs_serialized.h M src/commonlib/include/commonlib/helpers.h M src/console/die.c M src/console/post.c M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/car/romstage.c M src/cpu/intel/microcode/microcode.c M src/cpu/x86/16bit/entry16.inc M src/drivers/pc80/rtc/mc146818rtc_boot.c M src/include/console/console.h M src/include/console/uart.h M src/include/cpu/amd/mtrr.h M src/include/cpu/x86/cache.h M src/include/cpu/x86/cr.h M src/include/cpu/x86/msr.h M src/include/cpu/x86/mtrr.h M src/include/cpu/x86/tsc.h M src/include/device/device.h M src/include/device/mmio.h M src/include/device/pci_mmio_cfg.h M src/include/device/pci_ops.h M src/include/endian.h M src/include/halt.h M src/include/lib.h M src/include/pc80/mc146818rtc.h M src/include/stdbool.h M src/include/stddef.h M src/include/stdint.h M src/include/string.h M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/i82371eb/i82371eb.h M src/southbridge/intel/i82801gx/i82801gx.h M src/southbridge/intel/ibexpeak/pch.h M src/vendorcode/eltan/security/verified_boot/vboot_check.c 44 files changed, 11 insertions(+), 393 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/37334/1
diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S index 9d6f5a4..fef5ce9 100644 --- a/src/arch/x86/assembly_entry.S +++ b/src/arch/x86/assembly_entry.S @@ -13,8 +13,6 @@
#include <rules.h>
-#if !CONFIG(ROMCC_BOOTBLOCK) - /* * This path is for stages that are post bootblock. The gdt is reloaded * to accommodate platforms that are executing out of CAR. In order to @@ -60,26 +58,3 @@ /* Expect to never return. */ 1: jmp 1b - -#else - -/* This file assembles the start of the romstage program by the order of the - * includes. Thus, it's extremely important that one pays very careful - * attention to the order of the includes. */ - -#include <arch/x86/prologue.inc> -#include <cpu/x86/32bit/entry32.inc> -#include <cpu/x86/fpu_enable.inc> -#if CONFIG(SSE) -#include <cpu/x86/sse_enable.inc> -#endif - -/* - * The assembly.inc is generated based on the requirements of the mainboard. - * For example, for ROMCC boards the MAINBOARDDIR/romstage.c would be - * processed by ROMCC and added. In non-ROMCC boards the chipsets' - * cache-as-ram setup files would be here. - */ -#include <generated/assembly.inc> - -#endif diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index bd99c21..8872439 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -148,7 +148,7 @@ .data
/* This is the gdt for GCC part of coreboot. - * It is different from the gdt in ROMCC/ASM part of coreboot + * It is different from the gdt in ASM part of coreboot * which is defined in entry32.inc * * When the machine is initially started, we use a very simple diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 479067f..68475c1 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -45,7 +45,7 @@ #define ACPI_TABLE_CREATOR "COREBOOT" /* Must be exactly 8 bytes long! */ #define OEM_ID "COREv4" /* Must be exactly 6 bytes long! */
-#if !defined(__ASSEMBLER__) && !defined(__ACPI__) && !defined(__ROMCC__) +#if !defined(__ASSEMBLER__) && !defined(__ACPI__) #include <commonlib/helpers.h> #include <device/device.h> #include <uuid.h> diff --git a/src/arch/x86/include/arch/bootblock_romcc.h b/src/arch/x86/include/arch/bootblock_romcc.h deleted file mode 100644 index 827e40e..0000000 --- a/src/arch/x86/include/arch/bootblock_romcc.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cpu/x86/lapic/boot_cpu.c> - -#ifdef CONFIG_BOOTBLOCK_RESETS -#include CONFIG_BOOTBLOCK_RESETS -#endif - -#ifdef CONFIG_BOOTBLOCK_CPU_INIT -#include CONFIG_BOOTBLOCK_CPU_INIT -#endif -#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT -#include CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT -#endif -#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT -#include CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT -#endif - -#ifdef CONFIG_BOOTBLOCK_MAINBOARD_INIT -#include CONFIG_BOOTBLOCK_MAINBOARD_INIT -#else -static void bootblock_mainboard_init(void) -{ -#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT - bootblock_northbridge_init(); -#endif -#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT - bootblock_southbridge_init(); -#endif -#ifdef CONFIG_BOOTBLOCK_CPU_INIT - bootblock_cpu_init(); -#endif -} -#endif diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 50d636b..c8cf8c7 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -218,9 +218,6 @@ return CONFIG(CPU_INTEL_COMMON) || CONFIG(SOC_INTEL_COMMON); }
-#ifndef __ROMCC__ -/* romcc does not support anonymous structs. */ - struct device;
struct cpu_device_id { @@ -288,13 +285,11 @@ #define asmlinkage __attribute__((regparm(0)))
/* - * When not using a romcc bootblock the car_stage_entry() is the symbol - * jumped to for each stage after bootblock using cache-as-ram. + * The car_stage_entry() is the symbol jumped to for each stage + * after bootblock using cache-as-ram. */ asmlinkage void car_stage_entry(void);
-#endif - /* * Get processor id using cpuid eax=1 * return value in EAX register diff --git a/src/arch/x86/include/arch/hlt.h b/src/arch/x86/include/arch/hlt.h index 7b18f55..a3f5c85 100644 --- a/src/arch/x86/include/arch/hlt.h +++ b/src/arch/x86/include/arch/hlt.h @@ -14,16 +14,9 @@ #ifndef ARCH_HLT_H #define ARCH_HLT_H
-#if defined(__ROMCC__) -static void hlt(void) -{ - __builtin_hlt(); -} -#else static __always_inline void hlt(void) { asm("hlt"); } -#endif
#endif /* ARCH_HLT_H */ diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index d39bbb3..43cfc1b 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -21,39 +21,6 @@ * inb/inw/inl/outb/outw/outl and the "string versions" of the same * (insb/insw/insl/outsb/outsw/outsl). */ -#if defined(__ROMCC__) -static inline void outb(uint8_t value, uint16_t port) -{ - __builtin_outb(value, port); -} - -static inline void outw(uint16_t value, uint16_t port) -{ - __builtin_outw(value, port); -} - -static inline void outl(uint32_t value, uint16_t port) -{ - __builtin_outl(value, port); -} - - -static inline uint8_t inb(uint16_t port) -{ - return __builtin_inb(port); -} - - -static inline uint16_t inw(uint16_t port) -{ - return __builtin_inw(port); -} - -static inline uint32_t inl(uint16_t port) -{ - return __builtin_inl(port); -} -#else static inline void outb(uint8_t value, uint16_t port) { __asm__ __volatile__ ("outb %b0, %w1" : : "a" (value), "Nd" (port)); @@ -89,7 +56,6 @@ __asm__ __volatile__ ("inl %w1, %0" : "=a"(value) : "Nd" (port)); return value; } -#endif /* __ROMCC__ */
static inline void outsb(uint16_t port, const void *addr, unsigned long count) { diff --git a/src/arch/x86/include/arch/mmio.h b/src/arch/x86/include/arch/mmio.h index f271a97..efdbe27 100644 --- a/src/arch/x86/include/arch/mmio.h +++ b/src/arch/x86/include/arch/mmio.h @@ -34,13 +34,11 @@ return *((volatile uint32_t *)(addr)); }
-#ifndef __ROMCC__ static __always_inline uint64_t read64( const volatile void *addr) { return *((volatile uint64_t *)(addr)); } -#endif
static __always_inline void write8(volatile void *addr, uint8_t value) @@ -60,12 +58,10 @@ *((volatile uint32_t *)(addr)) = value; }
-#ifndef __ROMCC__ static __always_inline void write64(volatile void *addr, uint64_t value) { *((volatile uint64_t *)(addr)) = value; } -#endif
#endif /* __ARCH_MMIO_H__ */ diff --git a/src/arch/x86/include/arch/pci_mmio_cfg_romcc.h b/src/arch/x86/include/arch/pci_mmio_cfg_romcc.h deleted file mode 100644 index 36a88f1..0000000 --- a/src/arch/x86/include/arch/pci_mmio_cfg_romcc.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _PCI_MMIO_CFG_ROMCC_H -#define _PCI_MMIO_CFG_ROMCC_H - -#include <stdint.h> -#include <device/mmio.h> -#include <device/pci_type.h> - - -static __always_inline -uint8_t pci_mmio_read_config8(pci_devfn_t dev, uint16_t reg) -{ - void *addr; - addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | reg); - return read8(addr); -} - -static __always_inline -uint16_t pci_mmio_read_config16(pci_devfn_t dev, uint16_t reg) -{ - void *addr; - addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~1)); - return read16(addr); -} - -static __always_inline -uint32_t pci_mmio_read_config32(pci_devfn_t dev, uint16_t reg) -{ - void *addr; - addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~3)); - return read32(addr); -} - -static __always_inline -void pci_mmio_write_config8(pci_devfn_t dev, uint16_t reg, uint8_t value) -{ - void *addr; - addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | reg); - write8(addr, value); -} - -static __always_inline -void pci_mmio_write_config16(pci_devfn_t dev, uint16_t reg, uint16_t value) -{ - void *addr; - addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~1)); - write16(addr, value); -} - -static __always_inline -void pci_mmio_write_config32(pci_devfn_t dev, uint16_t reg, uint32_t value) -{ - void *addr; - addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~3)); - write32(addr, value); -} - -#endif /* _PCI_MMIO_CFG_ROMCC_H */ diff --git a/src/arch/x86/include/arch/pci_ops.h b/src/arch/x86/include/arch/pci_ops.h index 4278ed0..e706216 100644 --- a/src/arch/x86/include/arch/pci_ops.h +++ b/src/arch/x86/include/arch/pci_ops.h @@ -15,12 +15,6 @@ #define ARCH_I386_PCI_OPS_H
#include <arch/pci_io_cfg.h> - -#if defined(__ROMCC__) -/* Must come before <device/pci_mmio_cfg.h> */ -#include <arch/pci_mmio_cfg_romcc.h> -#endif - #include <device/pci_mmio_cfg.h>
#endif /* ARCH_I386_PCI_OPS_H */ diff --git a/src/commonlib/include/commonlib/cbfs_serialized.h b/src/commonlib/include/commonlib/cbfs_serialized.h index a4708e8..d3a18c6 100644 --- a/src/commonlib/include/commonlib/cbfs_serialized.h +++ b/src/commonlib/include/commonlib/cbfs_serialized.h @@ -187,11 +187,6 @@ uint32_t alignment; } __packed;
-/* - * ROMCC does not understand uint64_t, so we hide future definitions as they are - * unlikely to be ever needed from ROMCC - */ -#ifndef __ROMCC__
/*** Component sub-headers ***/
@@ -236,6 +231,4 @@ uint32_t len; } __packed;
-#endif /* __ROMCC__ */ - #endif /* _CBFS_SERIALIZED_H_ */ diff --git a/src/commonlib/include/commonlib/helpers.h b/src/commonlib/include/commonlib/helpers.h index ca3b3c5..f07b6c2 100644 --- a/src/commonlib/include/commonlib/helpers.h +++ b/src/commonlib/include/commonlib/helpers.h @@ -41,13 +41,10 @@ var_a op var_b ? var_a : var_b; \ })
-#ifdef __ROMCC__ /* romcc doesn't support __builtin_choose_expr() */ -#define __CMP(a, b, op) __CMP_UNSAFE(a, b, op) -#else + #define __CMP(a, b, op) __builtin_choose_expr( \ __builtin_constant_p(a) && __builtin_constant_p(b), \ __CMP_UNSAFE(a, b, op), __CMP_SAFE(a, b, op, __TMPNAME, __TMPNAME)) -#endif
#ifndef MIN #define MIN(a, b) __CMP(a, b, <) @@ -108,12 +105,8 @@ #define GHz (1000 * MHz)
#ifndef offsetof -#ifdef __ROMCC__ -#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) -#else #define offsetof(TYPE, MEMBER) __builtin_offsetof(TYPE, MEMBER) #endif -#endif
#define check_member(structure, member, offset) _Static_assert( \ offsetof(struct structure, member) == offset, \ diff --git a/src/console/die.c b/src/console/die.c index 76c456d..e57c4e4 100644 --- a/src/console/die.c +++ b/src/console/die.c @@ -15,8 +15,6 @@ #include <console/console.h> #include <halt.h>
-#ifndef __ROMCC__ - /* * The method should be overwritten in mainboard directory to signal that a * fatal error had occurred. On boards that do share the same EC and where the @@ -39,4 +37,3 @@ die_notify(); halt(); } -#endif diff --git a/src/console/post.c b/src/console/post.c index 64aa2a5..8c28ceb 100644 --- a/src/console/post.c +++ b/src/console/post.c @@ -24,8 +24,6 @@
/* Write POST information */
-/* someday romcc will be gone. */ -#ifndef __ROMCC__ /* Some mainboards have very nice features beyond just a simple display. * They can override this function. */ @@ -33,11 +31,6 @@ { }
-#else -/* This just keeps the number of #ifs to a minimum */ -#define mainboard_post(x) -#endif - #if CONFIG(CMOS_POST)
DECLARE_SPIN_LOCK(cmos_post_lock) diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index 5a668c4..4dee0a8 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -28,11 +28,8 @@ _cache_as_ram_setup:
bootblock_pre_c_entry: - -#if !CONFIG(ROMCC_BOOTBLOCK) movl $cache_as_ram, %esp /* return address */ jmp check_mtrr /* Check if CPU properly reset */ -#endif
cache_as_ram: post_code(0x20) diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index 1f8eb9a..bd6a5a9 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -71,19 +71,6 @@ /* We do not return here. */ }
-#if CONFIG(ROMCC_BOOTBLOCK) -/* This wrapper enables easy transition away from ROMCC_BOOTBLOCK - * keeping changes in cache_as_ram.S easy to manage. - */ -asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) -{ - timestamp_init(base_timestamp); - timestamp_add_now(TS_START_ROMSTAGE); - romstage_main(bist); -} -#endif - - /* We don't carry BIST from bootblock in a good location to read from. * Any error should have been reported in bootblock already. */ diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 80470bf..90138be 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -15,11 +15,7 @@
#include <stdint.h> #include <stddef.h> -#if !defined(__ROMCC__) #include <cbfs.h> -#else -#include <arch/cbfs.h> -#endif #include <arch/cpu.h> #include <console/console.h> #include <cpu/x86/msr.h> @@ -141,22 +137,11 @@ unsigned int x86_model, x86_family; msr_t msr;
-#ifdef __ROMCC__ - struct cbfs_file *microcode_file; - - microcode_file = walkcbfs_head((char *) MICROCODE_CBFS_FILE); - if (!microcode_file) - return NULL; - - ucode_updates = CBFS_SUBHEADER(microcode_file); - microcode_len = ntohl(microcode_file->len); -#else ucode_updates = cbfs_boot_map_with_leak(MICROCODE_CBFS_FILE, CBFS_TYPE_MICROCODE, µcode_len); if (ucode_updates == NULL) return NULL; -#endif
/* CPUID sets MSR 0x8B if a microcode update has been loaded. */ msr.lo = 0; @@ -201,8 +186,7 @@ microcode_len -= update_size; }
- /* ROMCC doesn't like NULL. */ - return (void *)0; + return NULL; }
void intel_update_microcode_from_cbfs(void) diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index e0babd5..f409db0 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -29,8 +29,6 @@
#include <arch/rom_segs.h>
-#if !CONFIG(ROMCC_BOOTBLOCK) || \ - CONFIG(SIPI_VECTOR_IN_ROM) /* Symbol _start16bit must be aligned to 4kB to start AP CPUs with * Startup IPI message without RAM. */ diff --git a/src/drivers/pc80/rtc/mc146818rtc_boot.c b/src/drivers/pc80/rtc/mc146818rtc_boot.c index 0ac06b3..aa3e0f1 100644 --- a/src/drivers/pc80/rtc/mc146818rtc_boot.c +++ b/src/drivers/pc80/rtc/mc146818rtc_boot.c @@ -12,11 +12,7 @@ */
#include <stdint.h> -#ifdef __ROMCC__ -#include <arch/cbfs.h> -#else #include <cbfs.h> -#endif #include <pc80/mc146818rtc.h> #if CONFIG(USE_OPTION_TABLE) #include <option_table.h> @@ -60,12 +56,8 @@ CONFIG(STATIC_OPTION_TABLE)) { size_t length = 128; const unsigned char *cmos_default = -#ifdef __ROMCC__ - walkcbfs("cmos.default"); -#else cbfs_boot_map_with_leak("cmos.default", CBFS_COMPONENT_CMOS_DEFAULT, &length); -#endif if (cmos_default) { size_t i; cmos_disable_rtc(); diff --git a/src/include/console/console.h b/src/include/console/console.h index 607c968..583420c 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -26,8 +26,6 @@ #define RAM_DEBUG (CONFIG(DEBUG_RAM_SETUP) ? BIOS_DEBUG : BIOS_NEVER) #define RAM_SPEW (CONFIG(DEBUG_RAM_SETUP) ? BIOS_SPEW : BIOS_NEVER)
-#ifndef __ROMCC__ - #include <console/vtxprintf.h>
void post_code(u8 value); @@ -101,11 +99,4 @@
int do_vprintk(int msg_level, const char *fmt, va_list args);
-#else - -static inline void romcc_printk(void) { } -#define printk(...) romcc_printk() - -#endif /* !__ROMCC__ */ - #endif /* CONSOLE_CONSOLE_H_ */ diff --git a/src/include/console/uart.h b/src/include/console/uart.h index aed67c2..162b110 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -55,7 +55,6 @@
uintptr_t uart_platform_base(int idx);
-#if !defined(__ROMCC__) static inline void *uart_platform_baseptr(int idx) { return (void *)uart_platform_base(idx); @@ -100,6 +99,4 @@ } #endif
-#endif /* __ROMCC__ */ - #endif /* CONSOLE_UART_H */ diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h index edbf7bb..906a7c0 100644 --- a/src/include/cpu/amd/mtrr.h +++ b/src/include/cpu/amd/mtrr.h @@ -38,7 +38,7 @@ #define TOP_MEM_MASK 0x007fffff #define TOP_MEM_MASK_KB (TOP_MEM_MASK >> 10)
-#if !defined(__ROMCC__) && !defined(__ASSEMBLER__) +#if !defined(__ASSEMBLER__)
#include <cpu/x86/msr.h>
diff --git a/src/include/cpu/x86/cache.h b/src/include/cpu/x86/cache.h index 713ca32..0331e27 100644 --- a/src/include/cpu/x86/cache.h +++ b/src/include/cpu/x86/cache.h @@ -23,28 +23,11 @@
#if !defined(__ASSEMBLER__)
-/* - * Need two versions because ROMCC chokes on certain clobbers: - * cache.h:29.71: cache.h:60.24: earlymtrr.c:117.23: romstage.c:144.33: - * 0x1559920 asm Internal compiler error: lhs 1 regcm == 0 - */ - -#if defined(__GNUC__) - static inline void wbinvd(void) { asm volatile ("wbinvd" ::: "memory"); }
-#else - -static inline void wbinvd(void) -{ - asm volatile ("wbinvd"); -} - -#endif - static inline void invd(void) { asm volatile("invd" ::: "memory"); diff --git a/src/include/cpu/x86/cr.h b/src/include/cpu/x86/cr.h index 0f14d54..0339aa3 100644 --- a/src/include/cpu/x86/cr.h +++ b/src/include/cpu/x86/cr.h @@ -20,12 +20,7 @@
#include <stdint.h>
-/* ROMCC apparently chokes certain clobber registers. */ -#if defined(__ROMCC__) -#define COMPILER_BARRIER -#else #define COMPILER_BARRIER "memory" -#endif
#ifdef __x86_64__ #define CRx_TYPE uint64_t diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 2710e7f..63cb8bd 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -81,21 +81,6 @@
#ifndef __ASSEMBLER__ #include <types.h> -#if defined(__ROMCC__) - -typedef __builtin_msr_t msr_t; - -static msr_t rdmsr(unsigned long index) -{ - return __builtin_rdmsr(index); -} - -static void wrmsr(unsigned long index, msr_t msr) -{ - __builtin_wrmsr(index, msr.lo, msr.hi); -} - -#else
typedef struct msr_struct { unsigned int lo; @@ -154,7 +139,6 @@ }
#endif /* CONFIG_SOC_SETS_MSRS */ -#endif /* __ROMCC__ */
/* Helpers for interpreting MC[i]_STATUS */
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 29256c8..0e7a2d1 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -53,7 +53,7 @@ #define MTRR_FIX_4K_F0000 0x26e #define MTRR_FIX_4K_F8000 0x26f
-#if !defined(__ASSEMBLER__) && !defined(__ROMCC__) +#if !defined(__ASSEMBLER__)
#include <stdint.h> #include <stddef.h> @@ -140,9 +140,9 @@ "1:" : "=r" (r) : "mr" (x)); return r; } -#endif /* !defined(__ASSEMBLER__) && !defined(__ROMCC__) */ +#endif /* !defined(__ASSEMBLER__)
-/* Align up/down to next power of 2, suitable for ROMCC and assembler +/* Align up/down to next power of 2, suitable for assembler too. Range of result 256kB to 128MB is good enough here. */ #define _POW2_MASK(x) ((x>>1)|(x>>2)|(x>>3)|(x>>4)|(x>>5)| \ (x>>6)|(x>>7)|(x>>8)|((1<<18)-1)) diff --git a/src/include/cpu/x86/tsc.h b/src/include/cpu/x86/tsc.h index c18f878..6943b93 100644 --- a/src/include/cpu/x86/tsc.h +++ b/src/include/cpu/x86/tsc.h @@ -28,7 +28,6 @@ return res; }
-#if !defined(__ROMCC__) /* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. * This code is used to prevent use of libgcc's umoddi3. */ @@ -42,7 +41,6 @@ tsc->hi = ((a >> 16) * (b >> 16)) + (tsc->hi >> 16); }
-/* Too many registers for ROMCC */ static inline unsigned long long rdtscll(void) { unsigned long long val; @@ -58,7 +56,6 @@ { return (((uint64_t)tstamp.hi) << 32) + tstamp.lo; } -#endif
/* Provided by CPU/chipset code for the TSC rate in MHz. */ unsigned long tsc_freq_mhz(void); diff --git a/src/include/device/device.h b/src/include/device/device.h index abcd0a4..e391291 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -2,13 +2,6 @@
#define DEVICE_H
-/* - * NOTICE: Header is ROMCC tentative. - * This header is incompatible with ROMCC and its inclusion leads to 'odd' - * build failures. - */ -#if !defined(__ROMCC__) - #include <device/resource.h> #include <device/path.h> #include <device/pci_type.h> @@ -330,6 +323,4 @@ void scan_generic_bus(struct device *bus); void scan_static_bus(struct device *bus);
-#endif /* !defined(__ROMCC__) */ - #endif /* DEVICE_H */ diff --git a/src/include/device/mmio.h b/src/include/device/mmio.h index 6596cf8..c2a6b83 100644 --- a/src/include/device/mmio.h +++ b/src/include/device/mmio.h @@ -19,7 +19,6 @@ #include <endian.h> #include <types.h>
-#ifndef __ROMCC__ /* * Reads a transfer buffer from 32-bit FIFO registers. fifo_stride is the * distance in bytes between registers (e.g. pass 4 for a normal array of 32-bit @@ -177,6 +176,4 @@ #define READ32_BITFIELD(addr, name) \ EXTRACT_BITFIELD(read32(addr), name)
-#endif /* !__ROMCC__ */ - #endif /* __DEVICE_MMIO_H__ */ diff --git a/src/include/device/pci_mmio_cfg.h b/src/include/device/pci_mmio_cfg.h index 30945f4..aa15970 100644 --- a/src/include/device/pci_mmio_cfg.h +++ b/src/include/device/pci_mmio_cfg.h @@ -20,7 +20,6 @@ #include <device/mmio.h> #include <device/pci_type.h>
-#if !defined(__ROMCC__)
/* By not assigning this to CONFIG_MMCONF_BASE_ADDRESS here we * prevent some sub-optimal constant folding. */ @@ -110,8 +109,6 @@ return (uint32_t *)&pcicfg(dev)->reg32[reg / sizeof(uint32_t)]; }
-#endif /* !defined(__ROMCC__) */ - #if CONFIG(MMCONF_SUPPORT)
#if CONFIG_MMCONF_BASE_ADDRESS == 0 diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h index 9d64f03..805c087 100644 --- a/src/include/device/pci_ops.h +++ b/src/include/device/pci_ops.h @@ -23,7 +23,6 @@ #include <device/pci_type.h> #include <arch/pci_ops.h>
-#ifndef __ROMCC__ void __noreturn pcidev_die(void);
static __always_inline pci_devfn_t pcidev_bdf(const struct device *dev) @@ -37,7 +36,6 @@ pcidev_die(); return pcidev_bdf(dev); } -#endif
#if defined(__SIMPLE_DEVICE__) #define ENV_PCI_SIMPLE_DEVICE 1 @@ -184,7 +182,6 @@ u16 pci_s_find_next_capability(pci_devfn_t dev, u16 cap, u16 last); u16 pci_s_find_capability(pci_devfn_t dev, u16 cap);
-#ifndef __ROMCC__ static __always_inline u16 pci_find_next_capability(const struct device *dev, u16 cap, u16 last) { @@ -196,6 +193,5 @@ { return pci_s_find_capability(PCI_BDF(dev), cap); } -#endif
#endif /* PCI_OPS_H */ diff --git a/src/include/endian.h b/src/include/endian.h index 8dc1854..72fb72d 100644 --- a/src/include/endian.h +++ b/src/include/endian.h @@ -84,7 +84,6 @@ #define clrbits_8(addr, clear) clrsetbits_8(addr, clear, 0) #define setbits_8(addr, set) setbits_8(addr, 0, set)
-#ifndef __ROMCC__ /* be16dec/be32dec/be64dec/le16dec/le32dec/le64dec family of functions. */ #define DEFINE_ENDIAN_DEC(endian, width) \ static inline uint##width##_t endian##width##dec(const void *p) \ @@ -174,6 +173,5 @@ { return le64_to_cpu(little_endian_64bits); } -#endif
#endif diff --git a/src/include/halt.h b/src/include/halt.h index 117c6c0..e2aa11c 100644 --- a/src/include/halt.h +++ b/src/include/halt.h @@ -17,14 +17,10 @@ #ifndef __HALT_H__ #define __HALT_H__
-#ifdef __ROMCC__ -#include <lib/halt.c> -#else /** * halt the system reliably */ void __noreturn halt(void); -#endif /* __ROMCC__ */
/* Power off the system. */ void poweroff(void); diff --git a/src/include/lib.h b/src/include/lib.h index 098d62d..d1bbe93 100644 --- a/src/include/lib.h +++ b/src/include/lib.h @@ -57,14 +57,12 @@ */ size_t hexstrtobin(const char *str, uint8_t *buf, size_t len);
-#if !defined(__ROMCC__) /* Count Leading Zeroes: clz(0) == 32, clz(0xf) == 28, clz(1 << 31) == 0 */ static inline int clz(u32 x) { return x ? __builtin_clz(x) : sizeof(x) * 8; } /* Integer binary logarithm (rounding down): log2(0) == -1, log2(5) == 2 */ static inline int log2(u32 x) { return sizeof(x) * 8 - clz(x) - 1; } /* Find First Set: __ffs(1) == 0, __ffs(0) == -1, __ffs(1<<31) == 31 */ static inline int __ffs(u32 x) { return log2(x & (u32)(-(s32)x)); } -#endif
/* Integer binary logarithm (rounding up): log2_ceil(0) == -1, log2(5) == 3 */ static inline int log2_ceil(u32 x) { return (x == 0) ? -1 : log2(x * 2 - 1); } diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index 6fa5e46..d1ade20 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -178,7 +178,6 @@ cmos_write((value >> (i << 3)) & 0xff, offset + i); }
-#if !defined(__ROMCC__) void cmos_init(bool invalid); void cmos_check_update_date(void);
@@ -187,9 +186,6 @@ unsigned int read_option_lowlevel(unsigned int start, unsigned int size, unsigned int def);
-#else /* defined(__ROMCC__) */ -#include <drivers/pc80/rtc/mc146818rtc_romcc.c> -#endif /* !defined(__ROMCC__) */ #define read_option(name, default) read_option_lowlevel(CMOS_VSTART_ ##name, \ CMOS_VLEN_ ##name, (default))
diff --git a/src/include/stdbool.h b/src/include/stdbool.h index 2eeb70e..d7f9e64 100644 --- a/src/include/stdbool.h +++ b/src/include/stdbool.h @@ -5,11 +5,8 @@
#include <stdint.h>
-#ifdef __ROMCC__ -typedef uint8_t bool; -#else + typedef _Bool bool; -#endif #define true 1 #define false 0
diff --git a/src/include/stddef.h b/src/include/stddef.h index a2c9c50..e318309 100644 --- a/src/include/stddef.h +++ b/src/include/stddef.h @@ -47,12 +47,10 @@ #define MAYBE_STATIC_BSS #endif
-#ifndef __ROMCC__ /* Provide a pointer to address 0 that thwarts any "accessing this is * undefined behaviour and do whatever" trickery in compilers. * Use when you _really_ need to read32(zeroptr) (ie. read address 0). */ extern char zeroptr[]; -#endif
#endif /* STDDEF_H */ diff --git a/src/include/stdint.h b/src/include/stdint.h index 67b0b0b..b534add 100644 --- a/src/include/stdint.h +++ b/src/include/stdint.h @@ -28,17 +28,14 @@ typedef signed int int32_t; typedef unsigned int uint32_t;
-#ifndef __ROMCC__ typedef signed long long int64_t; typedef unsigned long long uint64_t; -#endif
/* Types for 'void *' pointers */ typedef signed long intptr_t; typedef unsigned long uintptr_t;
/* Ensure that the widths are all correct */ -#ifndef __ROMCC__ _Static_assert(sizeof(int8_t) == 1, "Size of int8_t is incorrect"); _Static_assert(sizeof(uint8_t) == 1, "Size of uint8_t is incorrect");
@@ -53,13 +50,10 @@
_Static_assert(sizeof(intptr_t) == sizeof(void *), "Size of intptr_t is incorrect"); _Static_assert(sizeof(uintptr_t) == sizeof(void *), "Size of uintptr_t is incorrect"); -#endif
/* Maximum width integer types */ -#ifndef __ROMCC__ typedef int64_t intmax_t; typedef uint64_t uintmax_t; -#endif
/* Convenient typedefs */ typedef int8_t s8; @@ -71,10 +65,8 @@ typedef int32_t s32; typedef uint32_t u32;
-#ifndef __ROMCC__ typedef int64_t s64; typedef uint64_t u64; -#endif
/* Limits of integer types */ #define INT8_MIN ((int8_t)0x80) @@ -89,16 +81,12 @@ #define INT32_MAX ((int32_t)0x7FFFFFFF) #define UINT32_MAX ((uint32_t)0xFFFFFFFF)
-#ifndef __ROMCC__ #define INT64_MIN ((int64_t)0x8000000000000000) #define INT64_MAX ((int64_t)0x7FFFFFFFFFFFFFFF) #define UINT64_MAX ((uint64_t)0xFFFFFFFFFFFFFFFF) -#endif
-#ifndef __ROMCC__ #define INTMAX_MIN INT64_MIN #define INTMAX_MAX INT64_MAX #define UINTMAX_MAX UINT64_MAX -#endif
#endif /* STDINT_H */ diff --git a/src/include/string.h b/src/include/string.h index d3f09ff..bcfc111 100644 --- a/src/include/string.h +++ b/src/include/string.h @@ -4,9 +4,7 @@ #include <stddef.h> #include <stdlib.h>
-#if !defined(__ROMCC__) #include <console/vtxprintf.h> -#endif
/* Stringify a token */ #ifndef STRINGIFY @@ -19,10 +17,8 @@ void *memset(void *s, int c, size_t n); int memcmp(const void *s1, const void *s2, size_t n); void *memchr(const void *s, int c, size_t n); -#if !defined(__ROMCC__) int snprintf(char *buf, size_t size, const char *fmt, ...); int vsnprintf(char *buf, size_t size, const char *fmt, va_list args); -#endif char *strdup(const char *s); char *strconcat(const char *s1, const char *s2); size_t strnlen(const char *src, size_t max); diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 127fb61..089d458 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -90,10 +90,8 @@ int oc_pin; };
-#ifndef __ROMCC__ void pch_enable(struct device *dev); extern const struct southbridge_usb_port mainboard_usb_ports[14]; -#endif
void early_usb_init(const struct southbridge_usb_port *portmap);
diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h index 77931cb..d35b215 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.h +++ b/src/southbridge/intel/i82371eb/i82371eb.h @@ -19,10 +19,8 @@
#if !defined(__ACPI__)
-#ifndef __ROMCC__ #include <device/device.h> void i82371eb_enable(struct device *dev); -#endif
void i82371eb_hard_reset(void);
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 3d27faa..0516a7a 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -34,10 +34,8 @@ #ifndef __ACPI__ #define DEBUG_PERIODIC_SMIS 0
-#ifndef __ROMCC__ #include <device/device.h> void i82801gx_enable(struct device *dev); -#endif
void enable_smbus(void); void i82801gx_lpc_setup(void); diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 9ee76f2..5785ef1 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -89,11 +89,9 @@
void early_usb_init(const struct southbridge_usb_port *portmap);
-#ifndef __ROMCC__ extern const struct southbridge_usb_port mainboard_usb_ports[14]; #include <device/device.h> void pch_enable(struct device *dev); -#endif
#define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1 diff --git a/src/vendorcode/eltan/security/verified_boot/vboot_check.c b/src/vendorcode/eltan/security/verified_boot/vboot_check.c index bc502c9..461a847 100644 --- a/src/vendorcode/eltan/security/verified_boot/vboot_check.c +++ b/src/vendorcode/eltan/security/verified_boot/vboot_check.c @@ -276,13 +276,6 @@ { printk(BIOS_SPEW, "%s: processing early items\n", __func__);
- if (CONFIG(ROMCC_BOOTBLOCK) && - CONFIG(VENDORCODE_ELTAN_VBOOT_SIGNED_MANIFEST)) { - printk(BIOS_SPEW, "%s: check the manifest\n", __func__); - if (verified_boot_check_manifest() != 0) - die("invalid manifest"); - } - if (CONFIG(VENDORCODE_ELTAN_MBOOT)) { printk(BIOS_DEBUG, "mb_measure returned 0x%x\n", mb_measure(vboot_platform_is_resuming()));
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37334 )
Change subject: Drop ROMCC code and header guards ......................................................................
Patch Set 4: Code-Review+1
This change is ready for review.
Kyösti Mälkki has uploaded a new patch set (#5) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/37334 )
Change subject: Drop ROMCC code and header guards ......................................................................
Drop ROMCC code and header guards
Change-Id: I730f80afd8aad250f26534435aec24bea75a849c Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/arch/x86/assembly_entry.S M src/arch/x86/c_start.S M src/arch/x86/include/arch/acpi.h M src/arch/x86/include/arch/cpu.h M src/arch/x86/include/arch/hlt.h M src/arch/x86/include/arch/io.h M src/arch/x86/include/arch/mmio.h D src/arch/x86/include/arch/pci_mmio_cfg_romcc.h M src/arch/x86/include/arch/pci_ops.h M src/commonlib/include/commonlib/cbfs_serialized.h M src/commonlib/include/commonlib/helpers.h M src/console/die.c M src/console/post.c M src/cpu/x86/16bit/entry16.inc M src/include/console/console.h M src/include/console/uart.h M src/include/cpu/amd/mtrr.h M src/include/cpu/x86/cache.h M src/include/cpu/x86/cr.h M src/include/cpu/x86/msr.h M src/include/cpu/x86/mtrr.h M src/include/cpu/x86/tsc.h M src/include/device/device.h M src/include/device/mmio.h M src/include/device/pci_mmio_cfg.h M src/include/device/pci_ops.h M src/include/endian.h M src/include/halt.h M src/include/lib.h M src/include/stdbool.h M src/include/stddef.h M src/include/stdint.h M src/include/string.h M src/include/swab.h M src/vendorcode/eltan/security/verified_boot/vboot_check.c 35 files changed, 13 insertions(+), 299 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/37334/5
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37334 )
Change subject: Drop ROMCC code and header guards ......................................................................
Patch Set 5: Code-Review+1
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37334 )
Change subject: Drop ROMCC code and header guards ......................................................................
Patch Set 5: Code-Review+1
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37334 )
Change subject: Drop ROMCC code and header guards ......................................................................
Patch Set 5: Code-Review+2
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37334 )
Change subject: Drop ROMCC code and header guards ......................................................................
Patch Set 6: Code-Review+2
Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37334 )
Change subject: Drop ROMCC code and header guards ......................................................................
Drop ROMCC code and header guards
Change-Id: I730f80afd8aad250f26534435aec24bea75a849c Signed-off-by: Arthur Heymans arthur@aheymans.xyz Reviewed-on: https://review.coreboot.org/c/coreboot/+/37334 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-by: HAOUAS Elyes ehaouas@noos.fr --- M src/arch/x86/assembly_entry.S M src/arch/x86/c_start.S M src/arch/x86/include/arch/acpi.h M src/arch/x86/include/arch/cpu.h M src/arch/x86/include/arch/hlt.h M src/arch/x86/include/arch/io.h M src/arch/x86/include/arch/mmio.h D src/arch/x86/include/arch/pci_mmio_cfg_romcc.h M src/arch/x86/include/arch/pci_ops.h M src/commonlib/include/commonlib/cbfs_serialized.h M src/commonlib/include/commonlib/helpers.h M src/console/die.c M src/console/post.c M src/cpu/x86/16bit/entry16.inc M src/include/console/console.h M src/include/console/uart.h M src/include/cpu/amd/mtrr.h M src/include/cpu/x86/cache.h M src/include/cpu/x86/cr.h M src/include/cpu/x86/msr.h M src/include/cpu/x86/mtrr.h M src/include/cpu/x86/tsc.h M src/include/device/device.h M src/include/device/mmio.h M src/include/device/pci_mmio_cfg.h M src/include/device/pci_ops.h M src/include/endian.h M src/include/halt.h M src/include/lib.h M src/include/stdbool.h M src/include/stddef.h M src/include/stdint.h M src/include/string.h M src/include/swab.h M src/vendorcode/eltan/security/verified_boot/vboot_check.c 35 files changed, 13 insertions(+), 299 deletions(-)
Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved HAOUAS Elyes: Looks good to me, approved
diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S index 9d6f5a4..fef5ce9 100644 --- a/src/arch/x86/assembly_entry.S +++ b/src/arch/x86/assembly_entry.S @@ -13,8 +13,6 @@
#include <rules.h>
-#if !CONFIG(ROMCC_BOOTBLOCK) - /* * This path is for stages that are post bootblock. The gdt is reloaded * to accommodate platforms that are executing out of CAR. In order to @@ -60,26 +58,3 @@ /* Expect to never return. */ 1: jmp 1b - -#else - -/* This file assembles the start of the romstage program by the order of the - * includes. Thus, it's extremely important that one pays very careful - * attention to the order of the includes. */ - -#include <arch/x86/prologue.inc> -#include <cpu/x86/32bit/entry32.inc> -#include <cpu/x86/fpu_enable.inc> -#if CONFIG(SSE) -#include <cpu/x86/sse_enable.inc> -#endif - -/* - * The assembly.inc is generated based on the requirements of the mainboard. - * For example, for ROMCC boards the MAINBOARDDIR/romstage.c would be - * processed by ROMCC and added. In non-ROMCC boards the chipsets' - * cache-as-ram setup files would be here. - */ -#include <generated/assembly.inc> - -#endif diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index bd99c21..8872439 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -148,7 +148,7 @@ .data
/* This is the gdt for GCC part of coreboot. - * It is different from the gdt in ROMCC/ASM part of coreboot + * It is different from the gdt in ASM part of coreboot * which is defined in entry32.inc * * When the machine is initially started, we use a very simple diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 479067f..68475c1 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -45,7 +45,7 @@ #define ACPI_TABLE_CREATOR "COREBOOT" /* Must be exactly 8 bytes long! */ #define OEM_ID "COREv4" /* Must be exactly 6 bytes long! */
-#if !defined(__ASSEMBLER__) && !defined(__ACPI__) && !defined(__ROMCC__) +#if !defined(__ASSEMBLER__) && !defined(__ACPI__) #include <commonlib/helpers.h> #include <device/device.h> #include <uuid.h> diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 50d636b..c8cf8c7 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -218,9 +218,6 @@ return CONFIG(CPU_INTEL_COMMON) || CONFIG(SOC_INTEL_COMMON); }
-#ifndef __ROMCC__ -/* romcc does not support anonymous structs. */ - struct device;
struct cpu_device_id { @@ -288,13 +285,11 @@ #define asmlinkage __attribute__((regparm(0)))
/* - * When not using a romcc bootblock the car_stage_entry() is the symbol - * jumped to for each stage after bootblock using cache-as-ram. + * The car_stage_entry() is the symbol jumped to for each stage + * after bootblock using cache-as-ram. */ asmlinkage void car_stage_entry(void);
-#endif - /* * Get processor id using cpuid eax=1 * return value in EAX register diff --git a/src/arch/x86/include/arch/hlt.h b/src/arch/x86/include/arch/hlt.h index 7b18f55..a3f5c85 100644 --- a/src/arch/x86/include/arch/hlt.h +++ b/src/arch/x86/include/arch/hlt.h @@ -14,16 +14,9 @@ #ifndef ARCH_HLT_H #define ARCH_HLT_H
-#if defined(__ROMCC__) -static void hlt(void) -{ - __builtin_hlt(); -} -#else static __always_inline void hlt(void) { asm("hlt"); } -#endif
#endif /* ARCH_HLT_H */ diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index d39bbb3..43cfc1b 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -21,39 +21,6 @@ * inb/inw/inl/outb/outw/outl and the "string versions" of the same * (insb/insw/insl/outsb/outsw/outsl). */ -#if defined(__ROMCC__) -static inline void outb(uint8_t value, uint16_t port) -{ - __builtin_outb(value, port); -} - -static inline void outw(uint16_t value, uint16_t port) -{ - __builtin_outw(value, port); -} - -static inline void outl(uint32_t value, uint16_t port) -{ - __builtin_outl(value, port); -} - - -static inline uint8_t inb(uint16_t port) -{ - return __builtin_inb(port); -} - - -static inline uint16_t inw(uint16_t port) -{ - return __builtin_inw(port); -} - -static inline uint32_t inl(uint16_t port) -{ - return __builtin_inl(port); -} -#else static inline void outb(uint8_t value, uint16_t port) { __asm__ __volatile__ ("outb %b0, %w1" : : "a" (value), "Nd" (port)); @@ -89,7 +56,6 @@ __asm__ __volatile__ ("inl %w1, %0" : "=a"(value) : "Nd" (port)); return value; } -#endif /* __ROMCC__ */
static inline void outsb(uint16_t port, const void *addr, unsigned long count) { diff --git a/src/arch/x86/include/arch/mmio.h b/src/arch/x86/include/arch/mmio.h index f271a97..efdbe27 100644 --- a/src/arch/x86/include/arch/mmio.h +++ b/src/arch/x86/include/arch/mmio.h @@ -34,13 +34,11 @@ return *((volatile uint32_t *)(addr)); }
-#ifndef __ROMCC__ static __always_inline uint64_t read64( const volatile void *addr) { return *((volatile uint64_t *)(addr)); } -#endif
static __always_inline void write8(volatile void *addr, uint8_t value) @@ -60,12 +58,10 @@ *((volatile uint32_t *)(addr)) = value; }
-#ifndef __ROMCC__ static __always_inline void write64(volatile void *addr, uint64_t value) { *((volatile uint64_t *)(addr)) = value; } -#endif
#endif /* __ARCH_MMIO_H__ */ diff --git a/src/arch/x86/include/arch/pci_mmio_cfg_romcc.h b/src/arch/x86/include/arch/pci_mmio_cfg_romcc.h deleted file mode 100644 index 36a88f1..0000000 --- a/src/arch/x86/include/arch/pci_mmio_cfg_romcc.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _PCI_MMIO_CFG_ROMCC_H -#define _PCI_MMIO_CFG_ROMCC_H - -#include <stdint.h> -#include <device/mmio.h> -#include <device/pci_type.h> - - -static __always_inline -uint8_t pci_mmio_read_config8(pci_devfn_t dev, uint16_t reg) -{ - void *addr; - addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | reg); - return read8(addr); -} - -static __always_inline -uint16_t pci_mmio_read_config16(pci_devfn_t dev, uint16_t reg) -{ - void *addr; - addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~1)); - return read16(addr); -} - -static __always_inline -uint32_t pci_mmio_read_config32(pci_devfn_t dev, uint16_t reg) -{ - void *addr; - addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~3)); - return read32(addr); -} - -static __always_inline -void pci_mmio_write_config8(pci_devfn_t dev, uint16_t reg, uint8_t value) -{ - void *addr; - addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | reg); - write8(addr, value); -} - -static __always_inline -void pci_mmio_write_config16(pci_devfn_t dev, uint16_t reg, uint16_t value) -{ - void *addr; - addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~1)); - write16(addr, value); -} - -static __always_inline -void pci_mmio_write_config32(pci_devfn_t dev, uint16_t reg, uint32_t value) -{ - void *addr; - addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~3)); - write32(addr, value); -} - -#endif /* _PCI_MMIO_CFG_ROMCC_H */ diff --git a/src/arch/x86/include/arch/pci_ops.h b/src/arch/x86/include/arch/pci_ops.h index 4278ed0..e706216 100644 --- a/src/arch/x86/include/arch/pci_ops.h +++ b/src/arch/x86/include/arch/pci_ops.h @@ -15,12 +15,6 @@ #define ARCH_I386_PCI_OPS_H
#include <arch/pci_io_cfg.h> - -#if defined(__ROMCC__) -/* Must come before <device/pci_mmio_cfg.h> */ -#include <arch/pci_mmio_cfg_romcc.h> -#endif - #include <device/pci_mmio_cfg.h>
#endif /* ARCH_I386_PCI_OPS_H */ diff --git a/src/commonlib/include/commonlib/cbfs_serialized.h b/src/commonlib/include/commonlib/cbfs_serialized.h index a4708e8..d3a18c6 100644 --- a/src/commonlib/include/commonlib/cbfs_serialized.h +++ b/src/commonlib/include/commonlib/cbfs_serialized.h @@ -187,11 +187,6 @@ uint32_t alignment; } __packed;
-/* - * ROMCC does not understand uint64_t, so we hide future definitions as they are - * unlikely to be ever needed from ROMCC - */ -#ifndef __ROMCC__
/*** Component sub-headers ***/
@@ -236,6 +231,4 @@ uint32_t len; } __packed;
-#endif /* __ROMCC__ */ - #endif /* _CBFS_SERIALIZED_H_ */ diff --git a/src/commonlib/include/commonlib/helpers.h b/src/commonlib/include/commonlib/helpers.h index ca3b3c5..f07b6c2 100644 --- a/src/commonlib/include/commonlib/helpers.h +++ b/src/commonlib/include/commonlib/helpers.h @@ -41,13 +41,10 @@ var_a op var_b ? var_a : var_b; \ })
-#ifdef __ROMCC__ /* romcc doesn't support __builtin_choose_expr() */ -#define __CMP(a, b, op) __CMP_UNSAFE(a, b, op) -#else + #define __CMP(a, b, op) __builtin_choose_expr( \ __builtin_constant_p(a) && __builtin_constant_p(b), \ __CMP_UNSAFE(a, b, op), __CMP_SAFE(a, b, op, __TMPNAME, __TMPNAME)) -#endif
#ifndef MIN #define MIN(a, b) __CMP(a, b, <) @@ -108,12 +105,8 @@ #define GHz (1000 * MHz)
#ifndef offsetof -#ifdef __ROMCC__ -#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) -#else #define offsetof(TYPE, MEMBER) __builtin_offsetof(TYPE, MEMBER) #endif -#endif
#define check_member(structure, member, offset) _Static_assert( \ offsetof(struct structure, member) == offset, \ diff --git a/src/console/die.c b/src/console/die.c index 76c456d..e57c4e4 100644 --- a/src/console/die.c +++ b/src/console/die.c @@ -15,8 +15,6 @@ #include <console/console.h> #include <halt.h>
-#ifndef __ROMCC__ - /* * The method should be overwritten in mainboard directory to signal that a * fatal error had occurred. On boards that do share the same EC and where the @@ -39,4 +37,3 @@ die_notify(); halt(); } -#endif diff --git a/src/console/post.c b/src/console/post.c index 64aa2a5..8c28ceb 100644 --- a/src/console/post.c +++ b/src/console/post.c @@ -24,8 +24,6 @@
/* Write POST information */
-/* someday romcc will be gone. */ -#ifndef __ROMCC__ /* Some mainboards have very nice features beyond just a simple display. * They can override this function. */ @@ -33,11 +31,6 @@ { }
-#else -/* This just keeps the number of #ifs to a minimum */ -#define mainboard_post(x) -#endif - #if CONFIG(CMOS_POST)
DECLARE_SPIN_LOCK(cmos_post_lock) diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index e0babd5..40c0e99 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -29,13 +29,10 @@
#include <arch/rom_segs.h>
-#if !CONFIG(ROMCC_BOOTBLOCK) || \ - CONFIG(SIPI_VECTOR_IN_ROM) /* Symbol _start16bit must be aligned to 4kB to start AP CPUs with * Startup IPI message without RAM. */ .align 4096 -#endif .code16 .globl _start16bit .type _start16bit, @function diff --git a/src/include/console/console.h b/src/include/console/console.h index 607c968..583420c 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -26,8 +26,6 @@ #define RAM_DEBUG (CONFIG(DEBUG_RAM_SETUP) ? BIOS_DEBUG : BIOS_NEVER) #define RAM_SPEW (CONFIG(DEBUG_RAM_SETUP) ? BIOS_SPEW : BIOS_NEVER)
-#ifndef __ROMCC__ - #include <console/vtxprintf.h>
void post_code(u8 value); @@ -101,11 +99,4 @@
int do_vprintk(int msg_level, const char *fmt, va_list args);
-#else - -static inline void romcc_printk(void) { } -#define printk(...) romcc_printk() - -#endif /* !__ROMCC__ */ - #endif /* CONSOLE_CONSOLE_H_ */ diff --git a/src/include/console/uart.h b/src/include/console/uart.h index aed67c2..162b110 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -55,7 +55,6 @@
uintptr_t uart_platform_base(int idx);
-#if !defined(__ROMCC__) static inline void *uart_platform_baseptr(int idx) { return (void *)uart_platform_base(idx); @@ -100,6 +99,4 @@ } #endif
-#endif /* __ROMCC__ */ - #endif /* CONSOLE_UART_H */ diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h index edbf7bb..906a7c0 100644 --- a/src/include/cpu/amd/mtrr.h +++ b/src/include/cpu/amd/mtrr.h @@ -38,7 +38,7 @@ #define TOP_MEM_MASK 0x007fffff #define TOP_MEM_MASK_KB (TOP_MEM_MASK >> 10)
-#if !defined(__ROMCC__) && !defined(__ASSEMBLER__) +#if !defined(__ASSEMBLER__)
#include <cpu/x86/msr.h>
diff --git a/src/include/cpu/x86/cache.h b/src/include/cpu/x86/cache.h index 713ca32..0331e27 100644 --- a/src/include/cpu/x86/cache.h +++ b/src/include/cpu/x86/cache.h @@ -23,28 +23,11 @@
#if !defined(__ASSEMBLER__)
-/* - * Need two versions because ROMCC chokes on certain clobbers: - * cache.h:29.71: cache.h:60.24: earlymtrr.c:117.23: romstage.c:144.33: - * 0x1559920 asm Internal compiler error: lhs 1 regcm == 0 - */ - -#if defined(__GNUC__) - static inline void wbinvd(void) { asm volatile ("wbinvd" ::: "memory"); }
-#else - -static inline void wbinvd(void) -{ - asm volatile ("wbinvd"); -} - -#endif - static inline void invd(void) { asm volatile("invd" ::: "memory"); diff --git a/src/include/cpu/x86/cr.h b/src/include/cpu/x86/cr.h index 0f14d54..0339aa3 100644 --- a/src/include/cpu/x86/cr.h +++ b/src/include/cpu/x86/cr.h @@ -20,12 +20,7 @@
#include <stdint.h>
-/* ROMCC apparently chokes certain clobber registers. */ -#if defined(__ROMCC__) -#define COMPILER_BARRIER -#else #define COMPILER_BARRIER "memory" -#endif
#ifdef __x86_64__ #define CRx_TYPE uint64_t diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 2710e7f..63cb8bd 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -81,21 +81,6 @@
#ifndef __ASSEMBLER__ #include <types.h> -#if defined(__ROMCC__) - -typedef __builtin_msr_t msr_t; - -static msr_t rdmsr(unsigned long index) -{ - return __builtin_rdmsr(index); -} - -static void wrmsr(unsigned long index, msr_t msr) -{ - __builtin_wrmsr(index, msr.lo, msr.hi); -} - -#else
typedef struct msr_struct { unsigned int lo; @@ -154,7 +139,6 @@ }
#endif /* CONFIG_SOC_SETS_MSRS */ -#endif /* __ROMCC__ */
/* Helpers for interpreting MC[i]_STATUS */
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 29256c8..07db3cb 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -53,7 +53,7 @@ #define MTRR_FIX_4K_F0000 0x26e #define MTRR_FIX_4K_F8000 0x26f
-#if !defined(__ASSEMBLER__) && !defined(__ROMCC__) +#if !defined(__ASSEMBLER__)
#include <stdint.h> #include <stddef.h> @@ -140,9 +140,9 @@ "1:" : "=r" (r) : "mr" (x)); return r; } -#endif /* !defined(__ASSEMBLER__) && !defined(__ROMCC__) */ +#endif /* !defined(__ASSEMBLER__) */
-/* Align up/down to next power of 2, suitable for ROMCC and assembler +/* Align up/down to next power of 2, suitable for assembler too. Range of result 256kB to 128MB is good enough here. */ #define _POW2_MASK(x) ((x>>1)|(x>>2)|(x>>3)|(x>>4)|(x>>5)| \ (x>>6)|(x>>7)|(x>>8)|((1<<18)-1)) diff --git a/src/include/cpu/x86/tsc.h b/src/include/cpu/x86/tsc.h index c18f878..6943b93 100644 --- a/src/include/cpu/x86/tsc.h +++ b/src/include/cpu/x86/tsc.h @@ -28,7 +28,6 @@ return res; }
-#if !defined(__ROMCC__) /* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. * This code is used to prevent use of libgcc's umoddi3. */ @@ -42,7 +41,6 @@ tsc->hi = ((a >> 16) * (b >> 16)) + (tsc->hi >> 16); }
-/* Too many registers for ROMCC */ static inline unsigned long long rdtscll(void) { unsigned long long val; @@ -58,7 +56,6 @@ { return (((uint64_t)tstamp.hi) << 32) + tstamp.lo; } -#endif
/* Provided by CPU/chipset code for the TSC rate in MHz. */ unsigned long tsc_freq_mhz(void); diff --git a/src/include/device/device.h b/src/include/device/device.h index abcd0a4..e391291 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -2,13 +2,6 @@
#define DEVICE_H
-/* - * NOTICE: Header is ROMCC tentative. - * This header is incompatible with ROMCC and its inclusion leads to 'odd' - * build failures. - */ -#if !defined(__ROMCC__) - #include <device/resource.h> #include <device/path.h> #include <device/pci_type.h> @@ -330,6 +323,4 @@ void scan_generic_bus(struct device *bus); void scan_static_bus(struct device *bus);
-#endif /* !defined(__ROMCC__) */ - #endif /* DEVICE_H */ diff --git a/src/include/device/mmio.h b/src/include/device/mmio.h index 4007cff..524284a 100644 --- a/src/include/device/mmio.h +++ b/src/include/device/mmio.h @@ -37,7 +37,6 @@ #define clrbits32(addr, clear) clrsetbits32(addr, clear, 0) #define clrbits64(addr, clear) clrsetbits64(addr, clear, 0)
-#ifndef __ROMCC__ /* * Reads a transfer buffer from 32-bit FIFO registers. fifo_stride is the * distance in bytes between registers (e.g. pass 4 for a normal array of 32-bit @@ -195,6 +194,4 @@ #define READ32_BITFIELD(addr, name) \ EXTRACT_BITFIELD(read32(addr), name)
-#endif /* !__ROMCC__ */ - #endif /* __DEVICE_MMIO_H__ */ diff --git a/src/include/device/pci_mmio_cfg.h b/src/include/device/pci_mmio_cfg.h index 30945f4..aa15970 100644 --- a/src/include/device/pci_mmio_cfg.h +++ b/src/include/device/pci_mmio_cfg.h @@ -20,7 +20,6 @@ #include <device/mmio.h> #include <device/pci_type.h>
-#if !defined(__ROMCC__)
/* By not assigning this to CONFIG_MMCONF_BASE_ADDRESS here we * prevent some sub-optimal constant folding. */ @@ -110,8 +109,6 @@ return (uint32_t *)&pcicfg(dev)->reg32[reg / sizeof(uint32_t)]; }
-#endif /* !defined(__ROMCC__) */ - #if CONFIG(MMCONF_SUPPORT)
#if CONFIG_MMCONF_BASE_ADDRESS == 0 diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h index 9d64f03..805c087 100644 --- a/src/include/device/pci_ops.h +++ b/src/include/device/pci_ops.h @@ -23,7 +23,6 @@ #include <device/pci_type.h> #include <arch/pci_ops.h>
-#ifndef __ROMCC__ void __noreturn pcidev_die(void);
static __always_inline pci_devfn_t pcidev_bdf(const struct device *dev) @@ -37,7 +36,6 @@ pcidev_die(); return pcidev_bdf(dev); } -#endif
#if defined(__SIMPLE_DEVICE__) #define ENV_PCI_SIMPLE_DEVICE 1 @@ -184,7 +182,6 @@ u16 pci_s_find_next_capability(pci_devfn_t dev, u16 cap, u16 last); u16 pci_s_find_capability(pci_devfn_t dev, u16 cap);
-#ifndef __ROMCC__ static __always_inline u16 pci_find_next_capability(const struct device *dev, u16 cap, u16 last) { @@ -196,6 +193,5 @@ { return pci_s_find_capability(PCI_BDF(dev), cap); } -#endif
#endif /* PCI_OPS_H */ diff --git a/src/include/endian.h b/src/include/endian.h index f16f668..0f32b74 100644 --- a/src/include/endian.h +++ b/src/include/endian.h @@ -79,7 +79,6 @@ #define clrsetbits_le16(addr, clear, set) __clrsetbits(le, 16, addr, clear, set) #define clrsetbits_be16(addr, clear, set) __clrsetbits(be, 16, addr, clear, set)
-#ifndef __ROMCC__ /* be16dec/be32dec/be64dec/le16dec/le32dec/le64dec family of functions. */ #define DEFINE_ENDIAN_DEC(endian, width) \ static inline uint##width##_t endian##width##dec(const void *p) \ @@ -169,6 +168,5 @@ { return le64_to_cpu(little_endian_64bits); } -#endif
#endif diff --git a/src/include/halt.h b/src/include/halt.h index 117c6c0..e2aa11c 100644 --- a/src/include/halt.h +++ b/src/include/halt.h @@ -17,14 +17,10 @@ #ifndef __HALT_H__ #define __HALT_H__
-#ifdef __ROMCC__ -#include <lib/halt.c> -#else /** * halt the system reliably */ void __noreturn halt(void); -#endif /* __ROMCC__ */
/* Power off the system. */ void poweroff(void); diff --git a/src/include/lib.h b/src/include/lib.h index 098d62d..d1bbe93 100644 --- a/src/include/lib.h +++ b/src/include/lib.h @@ -57,14 +57,12 @@ */ size_t hexstrtobin(const char *str, uint8_t *buf, size_t len);
-#if !defined(__ROMCC__) /* Count Leading Zeroes: clz(0) == 32, clz(0xf) == 28, clz(1 << 31) == 0 */ static inline int clz(u32 x) { return x ? __builtin_clz(x) : sizeof(x) * 8; } /* Integer binary logarithm (rounding down): log2(0) == -1, log2(5) == 2 */ static inline int log2(u32 x) { return sizeof(x) * 8 - clz(x) - 1; } /* Find First Set: __ffs(1) == 0, __ffs(0) == -1, __ffs(1<<31) == 31 */ static inline int __ffs(u32 x) { return log2(x & (u32)(-(s32)x)); } -#endif
/* Integer binary logarithm (rounding up): log2_ceil(0) == -1, log2(5) == 3 */ static inline int log2_ceil(u32 x) { return (x == 0) ? -1 : log2(x * 2 - 1); } diff --git a/src/include/stdbool.h b/src/include/stdbool.h index 2eeb70e..d7f9e64 100644 --- a/src/include/stdbool.h +++ b/src/include/stdbool.h @@ -5,11 +5,8 @@
#include <stdint.h>
-#ifdef __ROMCC__ -typedef uint8_t bool; -#else + typedef _Bool bool; -#endif #define true 1 #define false 0
diff --git a/src/include/stddef.h b/src/include/stddef.h index a2c9c50..e318309 100644 --- a/src/include/stddef.h +++ b/src/include/stddef.h @@ -47,12 +47,10 @@ #define MAYBE_STATIC_BSS #endif
-#ifndef __ROMCC__ /* Provide a pointer to address 0 that thwarts any "accessing this is * undefined behaviour and do whatever" trickery in compilers. * Use when you _really_ need to read32(zeroptr) (ie. read address 0). */ extern char zeroptr[]; -#endif
#endif /* STDDEF_H */ diff --git a/src/include/stdint.h b/src/include/stdint.h index 67b0b0b..b534add 100644 --- a/src/include/stdint.h +++ b/src/include/stdint.h @@ -28,17 +28,14 @@ typedef signed int int32_t; typedef unsigned int uint32_t;
-#ifndef __ROMCC__ typedef signed long long int64_t; typedef unsigned long long uint64_t; -#endif
/* Types for 'void *' pointers */ typedef signed long intptr_t; typedef unsigned long uintptr_t;
/* Ensure that the widths are all correct */ -#ifndef __ROMCC__ _Static_assert(sizeof(int8_t) == 1, "Size of int8_t is incorrect"); _Static_assert(sizeof(uint8_t) == 1, "Size of uint8_t is incorrect");
@@ -53,13 +50,10 @@
_Static_assert(sizeof(intptr_t) == sizeof(void *), "Size of intptr_t is incorrect"); _Static_assert(sizeof(uintptr_t) == sizeof(void *), "Size of uintptr_t is incorrect"); -#endif
/* Maximum width integer types */ -#ifndef __ROMCC__ typedef int64_t intmax_t; typedef uint64_t uintmax_t; -#endif
/* Convenient typedefs */ typedef int8_t s8; @@ -71,10 +65,8 @@ typedef int32_t s32; typedef uint32_t u32;
-#ifndef __ROMCC__ typedef int64_t s64; typedef uint64_t u64; -#endif
/* Limits of integer types */ #define INT8_MIN ((int8_t)0x80) @@ -89,16 +81,12 @@ #define INT32_MAX ((int32_t)0x7FFFFFFF) #define UINT32_MAX ((uint32_t)0xFFFFFFFF)
-#ifndef __ROMCC__ #define INT64_MIN ((int64_t)0x8000000000000000) #define INT64_MAX ((int64_t)0x7FFFFFFFFFFFFFFF) #define UINT64_MAX ((uint64_t)0xFFFFFFFFFFFFFFFF) -#endif
-#ifndef __ROMCC__ #define INTMAX_MIN INT64_MIN #define INTMAX_MAX INT64_MAX #define UINTMAX_MAX UINT64_MAX -#endif
#endif /* STDINT_H */ diff --git a/src/include/string.h b/src/include/string.h index d3f09ff..bcfc111 100644 --- a/src/include/string.h +++ b/src/include/string.h @@ -4,9 +4,7 @@ #include <stddef.h> #include <stdlib.h>
-#if !defined(__ROMCC__) #include <console/vtxprintf.h> -#endif
/* Stringify a token */ #ifndef STRINGIFY @@ -19,10 +17,8 @@ void *memset(void *s, int c, size_t n); int memcmp(const void *s1, const void *s2, size_t n); void *memchr(const void *s, int c, size_t n); -#if !defined(__ROMCC__) int snprintf(char *buf, size_t size, const char *fmt, ...); int vsnprintf(char *buf, size_t size, const char *fmt, va_list args); -#endif char *strdup(const char *s); char *strconcat(const char *s1, const char *s2); size_t strnlen(const char *src, size_t max); diff --git a/src/include/swab.h b/src/include/swab.h index 57fe5a2..6a33b39 100644 --- a/src/include/swab.h +++ b/src/include/swab.h @@ -21,7 +21,7 @@
#include <stdint.h>
-#if defined(__ROMCC__) || ENV_ARMV4 +#if ENV_ARMV4 #define swab16(x) \ ((unsigned short)( \ (((unsigned short)(x) & (unsigned short)0x00ffU) << 8) | \ @@ -44,10 +44,10 @@ (((uint64_t)(x) & (uint64_t)0x0000ff0000000000ULL) >> 24) | \ (((uint64_t)(x) & (uint64_t)0x00ff000000000000ULL) >> 40) | \ (((uint64_t)(x) & (uint64_t)0xff00000000000000ULL) >> 56))) -#else /* __ROMCC__ || ENV_ARMV4 */ +#else /* ENV_ARMV4 */ #define swab16(x) ((uint16_t)__builtin_bswap16(x)) #define swab32(x) ((uint32_t)__builtin_bswap32(x)) #define swab64(x) ((uint64_t)__builtin_bswap64(x)) -#endif /* !(__ROMCC__ || ENV_ARMV4) */ +#endif /* !ENV_ARMV4 */
#endif /* _SWAB_H */ diff --git a/src/vendorcode/eltan/security/verified_boot/vboot_check.c b/src/vendorcode/eltan/security/verified_boot/vboot_check.c index bc502c9..461a847 100644 --- a/src/vendorcode/eltan/security/verified_boot/vboot_check.c +++ b/src/vendorcode/eltan/security/verified_boot/vboot_check.c @@ -276,13 +276,6 @@ { printk(BIOS_SPEW, "%s: processing early items\n", __func__);
- if (CONFIG(ROMCC_BOOTBLOCK) && - CONFIG(VENDORCODE_ELTAN_VBOOT_SIGNED_MANIFEST)) { - printk(BIOS_SPEW, "%s: check the manifest\n", __func__); - if (verified_boot_check_manifest() != 0) - die("invalid manifest"); - } - if (CONFIG(VENDORCODE_ELTAN_MBOOT)) { printk(BIOS_DEBUG, "mb_measure returned 0x%x\n", mb_measure(vboot_platform_is_resuming()));
-
Arthur Heymans (Code Review) -
HAOUAS Elyes (Code Review)
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Kyösti Mälkki (Code Review)