Attention is currently required from: Michał Żygowski, Paul Menzel, Angel Pons, Arthur Heymans. Michał Kopeć has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59808 )
Change subject: northbridge/amd/pi/00730F01: enable PARALLEL_MP ......................................................................
Patch Set 4:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59808/comment/29adb720_bb000d98 PS4, Line 7: src/
Please remove.
Done
File src/northbridge/amd/pi/00730F01/northbridge.c:
https://review.coreboot.org/c/coreboot/+/59808/comment/14ab29f6_c358d928 PS4, Line 874: sysconf_init
Looks like this is unused inside the cpu bus scanning now. […]
It's also used in `domain_read_resources`. I'm not sure where else this can be moved
https://review.coreboot.org/c/coreboot/+/59808/comment/da9e012f_bc688857 PS4, Line 900: /* The flash is now no longer cacheable. Reset to WP for performance. */ : mtrr_use_temp_range(OPTIMAL_CACHE_ROM_BASE, OPTIMAL_CACHE_ROM_SIZE, : MTRR_TYPE_WRPROT);
Any reason not to do this earlier, e.g. […]
If I do it in `pre_mp_init`, Linux complains about inconsistent MTRRs. I do it in `mp_init_cpus` because that's how other AMD platforms do it, but `post_mp_init` also works, so I'll move it there.
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Michał Kopeć (Code Review)