Varshit B Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39429 )
Change subject: [Test] [Do Not Merge]: Always on rails ......................................................................
[Test] [Do Not Merge]: Always on rails
Always turning on the Power Rails and keeping cam sensor out of reset.
Signed-off-by: Pandya, Varshit B varshit.b.pandya@intel.com Change-Id: I78508e82bee7954cae5069ebffea8f5fd35a5219 --- M src/mainboard/google/dedede/variants/baseboard/gpio.c M src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam0.asl M src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam1.asl 3 files changed, 24 insertions(+), 24 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/39429/1
diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index 62bf342..097afb4 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -71,13 +71,13 @@ PAD_NC(GPP_C23, DN_20K),
/* D12 : WCAM_RST_L */ - PAD_CFG_GPO(GPP_D12, 0, PLTRST), + PAD_CFG_GPO(GPP_D12, 1, PLTRST), /* D13 : EN_PP2800_CAMERA */ - PAD_CFG_GPO(GPP_D13, 0, PLTRST), + PAD_CFG_GPO(GPP_D13, 1, PLTRST), /* D14 : EN_PP1200_CAMERA */ - PAD_CFG_GPO(GPP_D14, 0, PLTRST), + PAD_CFG_GPO(GPP_D14, 1, PLTRST), /* D15 : UCAM_RST_L */ - PAD_CFG_GPO(GPP_D15, 0, PLTRST), + PAD_CFG_GPO(GPP_D15, 1, PLTRST), /* D16 : HP_INT_ODL*/ PAD_CFG_GPI_INT(GPP_D16, NONE, PLTRST, EDGE_BOTH), /* D17 : EN_SPK */ diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam0.asl b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam0.asl index c6b7cf1..7358eee 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam0.asl +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam0.asl @@ -40,30 +40,30 @@ { //Power signal are already ON //Assert Reset - CTXS(GPP_D12) - Sleep(5) + //CTXS(GPP_D12) + //Sleep(5) //Deassert Reset - STXS(GPP_D12) + //STXS(GPP_D12) } ELSE { //Enable PP1200 lane - STXS(GPP_D13) - //Enable PP2800 lane - STXS(GPP_D14) - Sleep(5) + //STXS(GPP_D13) + //Enable PP2800 lane + //STXS(GPP_D14) + //Sleep(5) //Assert Reset - CTXS(GPP_D12) - Sleep(5) + //CTXS(GPP_D12) + //Sleep(5) //Deassert Reset - STXS(GPP_D12) + //STXS(GPP_D12) } Store(1,STA0) } Method (_OFF, 0, Serialized) // _OFF_: Power Off { //Assert Reset - CTXS(GPP_D15) + //CTXS(GPP_D15) IF(STA1) { //Do nothing since the other sensor is ON @@ -72,9 +72,9 @@ ELSE { //Disable PP1200 lane - CTXS(GPP_D13) - //Disable PP2800 lane - CTXS(GPP_D14) + //CTXS(GPP_D13) + //Disable PP2800 lane + //CTXS(GPP_D14) //Do nothing since the other sensor is ON MCCT(0,0,1) // Clock 0, disable, 19.2MHz } diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam1.asl b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam1.asl index 77be947..8df60a8 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam1.asl +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam1.asl @@ -35,9 +35,9 @@ ELSE { //Enable PP1200 lane - STXS(GPP_D13) - //Enable PP2800 lane - STXS(GPP_D14) + STXS(GPP_D13) + //Enable PP2800 lane + STXS(GPP_D14) Sleep(5) //Assert Reset CTXS(GPP_D12) @@ -60,9 +60,9 @@ ELSE { //Disable PP1200 lane - CTXS(GPP_D13) - //Disable PP2800 lane - CTXS(GPP_D14) + CTXS(GPP_D13) + //Disable PP2800 lane + CTXS(GPP_D14) MCCT(1,0,1) // Clock 0, disable, 19.2MHz } Store(0,STA1)
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Varshit B Pandya (Code Review)